Granted Patent B1

US 7,432,750 · App. 11/296,786 · Granted Oct 7, 2008

Abstract

Claims (47)

1. A frequency synthesis circuit comprising:

a phase locked loop circuit for receiving a reference clock and a feedback clock and for generating an output clock comprising a frequency based on said reference clock and said feedback clock;

an interpolator control circuit for programming a frequency for said output clock by generating a control word during an increment interval, said interpolator control circuit for incrementing said control word by an increment size during said increment interval to generate a magnitude for the control word, the control word for providing a control value having said magnitude and a resolution,

the magnitude of the control value comprising an accumulation of the increment size during the increment duration, the resolution of the control value based on a range of the control value over the increment duration; and

an interpolator circuit, coupled in a feedback path to said phase locked loop circuit, for receiving said control word from said interpolator control circuit and for receiving said output clock and for generating said feedback clock by introducing a time delay in said output clock based on said control word that varies each increment interval so as to change said frequency of said output clock.

2. The circuit as set forth in claim 1 , wherein said interpolator control circuit comprises a circuit for controlling said variable time delay in said interpolator so as to generate a spread spectrum frequency clock as said output clock.

3. The circuit as set forth in claim 1 , wherein said interpolator control circuit comprises a circuit for receiving data, as an input, and for controlling said variable time delay in said interpolator so as to generate a frequency modulated signal of said data as said output clock.

4. The circuit as set forth in claim 3 , wherein said frequency modulated signal comprises a frequency shift key (“FSK”) modulated signal.

5. The circuit as set forth in claim 1 , wherein said interpolator control circuit comprises a circuit for controlling said variable time delay in said interpolator so as to generate a second reference clock as said output clock, wherein said second reference clock comprises a fixed frequency.

6. The frequency synthesis circuit as set forth in claim 1 , wherein the control word comprises a variable magnitude.

7. A spread spectrum clock synthesis circuit comprising:

a phase locked loop circuit for receiving a reference clock and a feedback clock and for generating a spread spectrum clock comprising a variable frequency based on said reference clock and said feedback clock;

an interpolator control circuit for generating a plurality of control words that correspond to a frequency pattern of said spread spectrum clock, the code words each comprising a magnitude and a resolution,

the magnitude of each code word comprising an accumulation of increment size during an increment duration, the increment size for modulating the frequency for the frequency pattern,

the resolution of each code word comprising a range of the magnitude of the code word during the increment duration; and

an interpolator circuit, coupled in a feedback path to said phase locked loop circuit, for receiving said control words and said spread spectrum clock and for generating said feedback clock by introducing a variable time delay in said spread spectrum clock, based on said control words, so as to vary said frequency of said spread spectrum clock.

8. The spread spectrum clock synthesis circuit as set forth in claim 7 , wherein said variable frequency of said spread spectrum clock comprises a frequency that varies linearly over a specified period.

9. The spread spectrum clock synthesis circuit as set forth in claim 7 , wherein said variable frequency of said spread spectrum clock comprises a frequency that cycles over a duration of time.

10. The spread spectrum clock synthesis circuit as set forth in claim 7 , wherein the control word comprises a variable magnitude.

11. A method for frequency synthesis comprising:

receiving a reference clock and a feedback clock in a phase locked loop circuit;

generating an output clock comprising a frequency based on said reference clock and said feedback clock;

generating a control signal during an increment interval, the control signal comprising a magnitude and a resolution,

the magnitude of the control signal corresponding to a change in the frequency of the output clock, the magnitude comprising an accumulation of increment size during an increment duration,

the resolution of the control signal comprising a range of the change in the magnitude of the control signal during the increment duration;

incrementing said control signal by an increment size during said increment interval;

receiving said output clock in a feedback path of said phase locked loop circuit; and

generating said feedback clock by introducing a variable time delay in said output clock based on said control signal so as to vary said frequency of said output clock every increment interval.

12. The method as set forth in claim 11 , wherein the control signal comprises a variable magnitude.

13. A clock generation circuit comprising:

a clock synthesis circuit for receiving a reference clock signal and for generating a first clock signal at a first frequency (f 1 ); and

a feedback circuit, coupled to said clock synthesis circuit, comprising a time variable phase shifter for receiving said first clock signal, as a reference, and for generating a second clock signal at a second frequency (f 2 ),

wherein a relationship between said first and second clock frequencies, expressed as

f

1

f

2

does not yield a rational number,

wherein said time variable phase shifter is configured to generate the second frequency f 2 by using the first frequency f 1 to provide a level of resolution having a relatively high granularity so as to provide a high bandwidth loop response for said feedback circuit; and

a control circuit, coupled to the feedback circuit, for controlling a variable time delay introduced by the time variable phase shifter, the control circuit for programming the second frequency for the second clock signal by generating a control signal during an increment interval, the control circuit for incrementing the control signal by an increment size during the increment interval to generate a magnitude for the control signal, the control signal for providing a control value having the magnitude and a resolution,

the magnitude of the control value comprising an accumulation of the increment size during the increment duration,

the resolution of the control value based on a range of the control value over the increment duration.

14. The clock generation circuit as set forth in claim 13 , wherein said first frequency comprises 9.953 Gigahertz (GHz) and said second frequency comprises 10.3125 GHz.

15. The clock generation circuit as set forth in claim 14 , further comprising an optical networking circuit that supports a SONET line rate of 9.953 Gigabits per second and a 10.3125 Gigabits per second, the optical networking circuit coupled to the clock synthesis circuit.

16. The clock generation circuit as set forth in claim 13 , wherein said time variable phase shifter comprises an interpolator circuit coupled to the feedback circuit, the interpolator circuit for receiving the control signal from the control circuit and for receiving the first clock signal and for generating the second clock signal by introducing a time delay in the second clock signal based on the control signal that varies each increment interval so as to change the frequency of the second clock signal.

17. The clock generation circuit as set forth in claim 13 , wherein said interpolator control signal comprises a clock offset word to define an offset between said first frequency and said second frequency.

18. The clock generation circuit as set forth in claim 13 , wherein the control signal comprises a variable magnitude.

Assignments (11)