Compound semiconductor and compound semiconductor device using the same
View Patent ↗A back electrode 6 is formed in the back of a Si single crystal substrate 2 of a compound semiconductor in which an n-type 3C-SiC single crystal buffer layer 3 having a thickness of 0.05-2 μm, a carrier concentration of 10 16 -10 21 /cm 3 , a hexagonal In w Ga x Al 1-w-x N single crystal buffer layer 4 (0≦w<1, 0≦x<1, w+x<1) having a thickness of 0.01-0.5 μm, and an n-type hexagonal In y Ga z Al 1-y-z N single crystal layer 5 (0≦y<1, 0<z≦1, y+z≦1) having a thickness of 0.1-5 μm and a carrier concentration of 10 11 -10 16 /cm 3 are stacked in order on an n-type Si single crystal substrate top 2 having a crystal-plane orientation {111}, a carrier concentration of 10 16 -10 21 /cm 3 , and a surface electrode 7 is formed on a surface of a hexagonal In y Ga z Al 1-y-z N single crystal layer 5 , so as to provide a compound semiconductor device which causes little energy loss and allows an high efficiency and a high breakdown voltage.
1. A compound semiconductor device in which a back electrode is formed on a back of an n-type Si single crystal substrate of the compound semiconductor device in which an n-type 3C-SiC single crystal buffer layer having a thickness of 0.05-2 μm and a carrier concentration of 10 16 -10 21 /cm 3 , a hexagonal In w Ga x Al 1-w-x N single crystal buffer layer having a thickness of 0.01-0.5 μm (0≦W<1, 0≦X<1, W+X<1), and an n-type hexagonal In y Ga z Al 1-y-z N single crystal layer (0≦Y<1, 0<Z≦1, Y+Z≦1) having a thickness of 0.1-5 μm and a carrier concentration of 10 11 -10 16 /cm 3 are stacked in order on an n-type Si single crystal substrate having a crystal-plane orientation {111} and a carrier concentration of 10 16 -10 21 /cm 3 , and a surface electrode is formed on a surface of the hexagonal In y Ga z Al 1-y-z N single crystal layer, and wherein an insulating layer is formed on a surface of the surface electrode and the surface of the hexagonal In y Ga z Al 1-y-z N, and an upper electrode is stacked on said insulating layer.
2. A compound semiconductor device as claimed in claim 1 , wherein said back electrode and surface electrode are each formed of a metal including at least one of Al, Ti, In, Au, Ni, Pt, W, and Pd, the back electrode is an ohmic electrode and the surface electrode is a Schottky electrode, and ohmic junctions formed between hexagonal In w Ga x Al 1-w-x N single crystal buffer layer, and hexagonal In y Ga z Al 1-y-z N single crystal layer when W=Y, X=Z.
3. A compound semiconductor device as claimed in claim 1 , wherein said back electrode and surface electrode are each formed of a metal including at least one of Al, Ti, In, Au, Ni, Pt, W, and Pd, the back electrode is an ohmic electrode, the surface electrode is an ohmic electrode, and heterojunctions form between hexagonal In w Ga x Al 1-w-x N single crystal buffer layer, and hexagonal In y Ga z Al 1-y-z N single crystal layer when W≠Y, X≠Z.
4. A compound semiconductor device as claimed in claim 1 , wherein at least two of said surface electrodes are provided and each formed of a metal including at least one of Al, Ti, In, Au, Ni, Pt, W, and Pd, and wherein at least one of the surface electrode is an ohmic electrode and the remaining surface electrode is a Schottky electrode.
5. A compound semiconductor device as claimed in claim 1 , wherein an area ratio of said surface electrode to each of said 3C-SiC single crystal buffer layer, hexagonal In w Ga x Al 1-w-x N single crystal buffer layer, and hexagonal In y Ga z Al 1-y-z N single crystal layer is 0.2-0.9.