IP Library Granted Patent US 7,981,726
Granted Patent B2
US 7,981,726 · App. 11/301,606 · Granted Jul 19, 2011

Copper plating connection for multi-die stack in substrate package

Assignee: Intel Corporation
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,981,726
App. No.
11/301,606
Granted
Jul 19, 2011
Kind
B2
Abstract

An embodiment of the present invention is a technique to construct a multi-die package. A stack of dice is formed from a base substrate in a package. The dice are positioned one on top of another and have copper plated segments for die interconnection. The dice are interconnected using copper plating to connect the copper plated segments.

Claims (31)

1. A method comprising:

forming a first layer having a first die on a base substrate in a package;

forming a next layer having a next die on the first layer, the dice having copper plated interconnects for die interconnection, wherein the copper plated interconnects are directly attached to the die;

interconnecting the dice using a substantially vertical interconnecting column comprising copper plating to connect the copper plated interconnects;

forming a first photo-resist layer of a dielectric material on the next layer;

attaching a final die to the first photo-resist layer;

forming a second photo-resist layer on the final die and the first photo-resist layer;

forming copper on the second photo-resist layer for substrate and die interconnection; and

forming a third photo-resist layer on the second photo-resist layer having at least an open pad connection for interconnection with a component or a board.

2. The method of claim 1 wherein forming the first layer comprises:

drilling the base substrate according to a first interconnection pattern;

plating the base substrate with copper;

attaching the first die to the plated base substrate;

coating and developing a photo-resist layer of a dielectric material on the first die and the plated base substrate; and

plating the developed photo-resist layer with copper for substrate and die interconnection to form the first layer.

3. The method of claim 1 wherein forming the next layer comprises:

coating and developing a first photo-resist layer of a dielectric material on a previous layer;

attaching the next die to the developed first photo-resist layer;

coating and developing a second photo-resist layer on the next die and the developed first photo-resist layer; and

plating the developed second photo-resist layer with copper for substrate and die interconnection to form the next layer.

4. The method of claim 1 wherein interconnecting further comprises:

forming substantially vertical vias on the copper plate interconnects; and filling the substantially vertical vias with copper to connect the copper plate interconnects.

5. A method comprising:

forming a first layer having a first die on a base substrate in a package;

forming a next layer having a next die on the first layer, the dice having copper plated interconnects for die interconnection, wherein the copper plated interconnects are directly attached to the die;

interconnecting the dice using a substantially vertical interconnecting column comprising copper plating to connect the copper plated interconnects;

coating and developing a first photo-resist layer of a dielectric material on a previous layer;

attaching the final die to the developed first photo-resist layer;

coating and developing a second photo-resist layer on the final die and the developed first photo-resist layer;

plating the developed second photo-resist layer with copper for substrate and die interconnection to form the final layer; and

coating and developing a third photo-resist layer on the plated second photo-resist layer having at least an open pad connection for interconnection with a component or a board.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 18, 2025
From: INTEL CORPORATION
To: SK HYNIX NAND PRODUCT SOLUTIONS CORP. (DBA SOLIDIGM)
Reel/Frame 072890/0186 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 12, 2005
From: TANG, JOHN J.; XU, HENRY; LI, JIANMIN; ZENG, XIANG YIN
To: INTEL CORPORATION
Reel/Frame 017355/0450 →
Continuity (1)
Related Publication 20070132082A1 · Jun 14, 2007