Neo-wafer device comprised of multiple singulated integrated circuit die
A neo-wafer made from integrated circuit die and methods for making a neo-wafer are disclosed. Recesses are formed on a substrate and a dielectric layer with conductive pads is created for the receiving of one or more die. Die are flip-chip bonded to the conductive pads and all voids under-filled. The neo-wafer is thinned to expose the dielectric and the conductive pads exposed, creating a neo-wafer.
1 . A neo-wafer comprised of:
A photo-imagable substrate having a first wafer surface and a second wafer surface and comprising a plurality of recesses defined there-through;
a dielectric layer substantially coplanar with said first surface and defined within said plurality of recesses;
at least one integrated circuit die disposed within said plurality of recesses and upon said dielectric layer, each of said integrated circuit die comprising at least one I/O pad;
an electrically conductive structure comprising a solder ball and an electrically conductive pad in electrical connection with said I/O pad;
said plurality of recesses substantially filled with an underfill material whereby said integrated circuit die and said electrically conductive structures are encapsulated within said plurality of recesses; and,
at least one via defined in said dielectric layer exposing said electrically conductive structure on said first wafer surface for the routing of an electronic signal to or from said I/O pad.