IP Library Granted Patent US 7,488,660
Granted Patent B2
US 7,488,660 · App. 11/307,759 · Granted Feb 10, 2009

Extended raised source/drain structure for enhanced contact area and method for forming extended raised source/drain structure

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Quick Facts
Patent No.
US 7,488,660
App. No.
11/307,759
Granted
Feb 10, 2009
Kind
B2
Abstract

A semiconductor device comprises a gate electrode stack having sidewalls and a top surface with a gate dielectric layer and the gate electrode, and LDD/LDS regions in the substrate aligned with the stack. Conformal L-shaped etch-stop layers with a thickness from about 50 Å to about 200 Å are formed with a vertical leg on the sidewalls of the stack and a horizontal leg reaching over the LDD/LDS regions next to the stack. RSD regions are formed in contact with the substrate aside from the etch-stop layers. The RSD regions cover the horizontal leg of the etch-stop layer and cover at least a portion of the vertical leg of the etch-stop layer on the sidewall of the gate electrode.

Claims (34)

1. A method for forming a structure in a semiconductor substrate, said structure including a gate electrode stack of a gate dielectric layer and a gate electrode formed over said substrate, and raised source/drain junctions, said method including the steps comprising:

forming said gate electrode stack comprising said gate dielectric layer and said gate electrode on said substrate with said gate electrode stack having sidewalls and a top surface;

forming Lightly Doped Drain/Doped Source (LDD/LDS) regions in said substrate self-aligned with said gate electrode;

forming a conformal etch-stop layer on said device;

forming sidewall spacers having a given width over said etch-stop layer on said sidewalls of said gate electrode stack;

etching away portions of said etch-stop layer unprotected by said sidewall spacers; and

forming Raised Source/Drain (RSD) regions on said substrate over exposed portions of said LDD/LDS regions in said substrate and covering said etch-stop layer over at least a portion of said sidewalls of said gate electrode.

2. The method of claim 1 , including removing said sidewall spacers prior to said step of forming said RSD regions.

3. The method of claim 1 , including as follows:

forming source/drain regions in said substrate after forming said sidewall spacers; and

then removing said sidewall spacers prior to said step of forming said RSD regions.

4. The method of claim 1 , including as follows:

retaining said sidewall spacers prior to said step of forming said RSD regions; and

incorporating said sidewall spacers in said RSD regions.

5. The method of claim 1 , including as follows:

forming source/drain regions in said substrate after forming said sidewall spacers; and

then said sidewall spacers are incorporated into said RSD regions.

6. The method of claim 1 , wherein:

L-shaped portions of said etch-stop layer remain on said sidewalls of said gate electrode stack extending laterally from gate electrode stack by said given width of said spacers; and

said RSD are formed by epitaxial growth of silicon over said substrate and over a portion of said etch-stop layer into juxtaposition with said sidewalls.

7. The method of claim 1 , wherein:

L-shaped portions of said etch-stop layer remain on said sidewalls of said gate electrode stack extending laterally from gate electrode stack by said given width of said spacers; and

forming said RSD regions by blanket deposition of RSD silicon covering said substrate and said spacers followed by etching back said RSD silicon and doping thereof.

8. The method of claim 1 including:

forming said sidewall spacers from silicon nitride;

subsequently performing said step of etching away portions of said etch-stop layer unprotected by said sidewall spacers;

then removing said sidewall spacers; and

then growing said RSD regions over said substrate.

9. The method of claim 1 , including:

forming said sidewall spacers from polysilicon;

subsequently performing said step of etching away portions of said etch-stop layer unprotected by said sidewall spacers;

then depositing a blanket layer of polysilicon; and

then etching back said polysilicon to form said RSD regions.

10. The method of claim 1 wherein said etch-stop layer has a thickness within a range from a minimum thickness of about 50Å to a maximum thickness of about 200Å .

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 22, 2017
From: GLOBALFOUNDRIES INC.
To: AURIGA INNOVATIONS, INC.
Reel/Frame 041777/0233 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 5, 2015
From: GLOBALFOUNDRIES U.S. 2 LLC; GLOBALFOUNDRIES U.S. INC.
To: GLOBALFOUNDRIES INC.
Reel/Frame 036779/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 3, 2015
From: INTERNATIONAL BUSINESS MACHINES CORPORATION
To: GLOBALFOUNDRIES U.S. 2 LLC
Reel/Frame 036550/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 21, 2006
From: DYER, THOMAS W.; FANG, SUNFEI
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 017197/0140 →