Erasing method for non-volatile memory
View Patent ↗An erasing method for a non-volatile memory is provided. The method includes the following two major steps. (a) A first voltage is applied to the odd-numbered select gates of each memory row and a second voltage is applied to the even-numbered select gates of each memory row such that the voltage difference between the first voltage and the second voltage is large enough for the electrons injected into the floating gate of the memory cells to be removed via the select gate. (b) A switchover operation is performed so that the first voltage is applied to the even-numbered select gates of each memory row and the second voltage is applied to the odd-numbered select gates of each memory row such that the electrons injected into the floating gates of the memory cells are pulled away via the select gates to turn the memory cells into an erased state.
1. An erasing method for a non-volatile memory, suitable for a memory cell array having a plurality of memory cell rows, wherein memory cells in each memory cell row are serially connected together between a source region, and a select gate is disposed between every two adjacent memory cells, between the memory cell closest to the source region and the source region, and between the memory cell closest to the drain region and the drain region respectively, wherein each memory cell includes at least a tunneling dielectric layer, a floating gate and a control gate, the method comprising:
(a) applying a first voltage to odd-numbered select gates of the memory cell row and applying a second voltage to even-numbered select gates of the memory cell row, wherein a voltage difference between the first voltage and the second voltage is large enough for electrons injected into the floating gate of the memory cells to be removed via the select gates; and
(b) performing a switchover action such that the first voltage and the second voltage are respectively applied to the even-numbered select gates and the odd-numbered select gates, and that the electrons injected into the floating gate of the memory cell are pulled away via the select gates to turn the memory cells in an erased state.
2. The erasing method of claim 1 , wherein after performing the step (a), the method further comprises checking whether the memory cells of each memory cell row has any erasing failure, and if at least one of the memory cells in the memory cell row has an erasing failure, the switchover action in step (b) is performed so that the electrons injected into the floating gate of the memory cells are be pulled away via the select gates to turn the memory cells into an erased state.
3. The erasing method of claim 1 , wherein the first voltage is between about 10V to 11V.
4. The erasing method of claim 3 , wherein the second voltage is 0V.
5. The erasing method of claim 1 , wherein the first voltage is 0V.
6. The erasing method of claim 5 , wherein the second voltage is between about 10V to 11V.
7. An erasing method for a non-volatile memory, suitable for a memory cell array having a plurality of memory cell rows, wherein memory cells in each memory cell row are serially connected together between a source region, and a select gate is disposed between every two adjacent memory cells, between the memory cell closest to the source region and the source region, and between the memory cell closest to the drain region and the drain region respectively, wherein each memory cell includes at least a tunneling dielectric layer, a floating gate and a control gate, the method comprising:
(a) applying a first voltage to odd-numbered select gates of the memory cell row and applying a second voltage to even-numbered select gates of the memory cell row, wherein a voltage difference between the first voltage and the second voltage is large enough for electrons injected into the floating gate of the memory cells to be removed via the select gates; and
(b) performing a switchover action such that a third voltage instead of the second voltage is applied to the even-numbered select gates, and that the electrons injected into the floating gate of the memory cell are pulled away via the select gates to turn the memory cells in an erased state.
8. The erasing method of claim 7 , wherein after performing the step (a), the method further comprises checking whether the memory cells of each memory cell row has any erasing failure, and if at least one of the memory cells in the memory cell row has an erasing failure, the switchover action in step (b) is performed so that the electrons injected into the floating gate of the memory cells are pulled away via the select gates to turn the memory cells into an erased state.
9. The erasing method of claim 7 , wherein the first voltage is between about 10V to 11V.
10. The erasing method of claim 9 , wherein the second voltage is 0V.
11. The erasing method of claim 9 , wherein the third voltage is equal to the first voltage.
12. The erasing method of claim 9 , wherein the third voltage is between about 10V to 11V.
13. The erasing method of claim 7 , wherein after performing the step (a), the method further comprises checking whether the memory cells of each memory cell row has any erasing failure, and if at least one of the memory cells in the memory cell row has an erasing failure, the switchover action in step (b) is performed so that a third voltage instead of the first voltage is applied to the even-numbered select gates of the memory cell row and the electrons injected into the floating gate of the memory cells are pulled away via the select gates to turn the memory cells into an erased state.
14. The erasing method of claim 13 , wherein the first voltage is 0V.
15. The erasing method of claim 14 , wherein the second voltage is between about 10V to 11V.
16. The erasing method of claim 14 , wherein the third voltage is equal to the second voltage.
17. The erasing method of claim 14 , wherein the third voltage is between about 10V to 11V.