Gate layouts for transistors
View Patent ↗A transistor and a method of fabricating the transistor are provided. The transistor includes a semiconductor material comprising drain regions and source regions formed in alternating rows or columns. The transistor also includes polysilicon chains overlaying the top of the semiconductor material, disconnected from and substantially parallel to one another, and separating the drain regions from the source regions. The method includes providing a semiconductor material, growing a first insulating layer on top of the semiconductor material, depositing a polysilicon layer on top of the first insulating layer, defining a plurality of chains in the polysilicon layer, the plurality of chains being disconnected from and substantially parallel to one another, and forming a plurality of drain regions and a plurality of source regions in the semiconductor material in alternating rows or columns. The plurality of chains separates the plurality of drain regions from the plurality of source regions.
1. A method of fabricating a transistor, the method comprising:
providing a semiconductor material having a top surface;
growing a first insulating layer on the top surface of the semiconductor material;
depositing a polysilicon layer on top of the first insulating layer, the first insulating layer insulating the polysilicon layer from the semiconductor material;
defining a plurality of chains in the polysilicon layer, the plurality of chains being disconnected from and substantially parallel to one another; and
forming a plurality of drain regions and a plurality of source regions in the semiconductor material, the plurality of drain regions and the plurality of source regions being formed in alternating rows or columns, wherein the plurality of chains separates the plurality of drain regions from the plurality of source regions.
2. The method of claim 1 , wherein at least one of the plurality of chains spans only one row or column of source regions and two rows or columns of drain regions or only one row or column of drain regions and two rows or columns of source regions.
3. The method of claim 1 , wherein at least one of the drain regions and at least one of the source regions are open.
4. The method of claim 1 , wherein each of the plurality of chains comprises a plurality of links.
5. The method of claim 4 , wherein at least one of the plurality of links approximates one of a diamond shape, a propeller shape, a rectangular shape, an elliptical shape, a circular shape, a rectangular shape, a V-shape, a U-shape, and a C-shape.
6. The method of claim 1 , wherein the semiconductor material is a well region of a first conductivity type and the plurality of drains regions and the plurality of source regions are of a second conductivity type.
7. The method of claim 6 , wherein the first conductivity type is an N-type or a P-type.
8. The method of claim 1 , wherein the semiconductor material is an epitaxial layer.
9. The method of claim 1 , further comprising:
defining at least one extension in the polysilicon layer, the at least one extension being connected to one end of each of the plurality of chains.
10. The method of claim 1 , further comprising:
forming a salicide on a surface of the plurality of drain regions and the plurality of source regions.
11. The method of claim 1 , further comprising:
growing a second insulating layer on top of the plurality of chains, the plurality of drain regions, and the plurality of source regions;
creating a plurality of contact openings in the second insulating layer;
depositing a metal layer on top of the second insulating layer; and
forming a strip in the metal layer over each row or column of drain regions and each row or column of source regions to contact the plurality of drain regions and the plurality of source regions.
12. The method of claim 11 , further comprising:
forming at least one gate plate in the metal layer to contact one end of each of the plurality of chains.