Method of manufacturing a high voltage semiconductor device including a deep well and a gate oxide layer simultaneously
View Patent ↗A method of manufacturing a high voltage semiconductor device including forming a P-type region implanted with P-type impurities and an N-type region implanted with N-type impurities in a silicon substrate. The method further includes forming a silicon nitride layer pattern and a pad oxide layer pattern to expose a surface of the silicon substrate, forming a trench by etching the exposed silicon substrate using the silicon nitride layer pattern as an etch mask, forming a trench oxide layer pattern in the trench by removing the silicon nitride layer pattern and the pad oxide layer pattern, and simultaneously forming a deep P-well and a deep N-well by driving P-type impurities in the P-type region and N-type impurities in the N-type region into the silicon substrate, while forming a gate oxide layer on a silicon substrate including the trench oxide layer pattern.
1. A method of manufacturing a high voltage semiconductor device, comprising:
forming a buffer oxide layer on the silicon substrate;
forming a first mask pattern to expose a first region of the buffer oxide layer;
forming the P-type region in the silicon substrate by implanting P-type impurities using the first mask pattern as an ion implantation mask;
removing the first mask pattern;
forming a second mask pattern to expose a second region of the buffer oxide layer; and
forming the N-type region in the silicon substrate by implanting N-type impurities using the second mask pattern as an ion implantation mask;
forming a silicon nitride layer pattern and a pad oxide layer pattern to expose a surface of the silicon substrate;
forming a trench by etching the exposed silicon substrate using the silicon nitride layer pattern as an etch mask;
forming a trench oxide layer pattern in the trench, comprising:
forming a trench oxide layer so as to fill in the trench;
performing chemical mechanical polishing to the trench oxide layer so as to expose a surface of the silicon nitride layer pattern; and
removing the silicon nitride layer pattern and pad oxide layer pattern by etching them; and
simultaneously forming a deep P-well and a deep N-well by driving P-type impurities in the P-type region and N-type impurities in the N-type region into the silicon substrate, respectively, while forming a gate oxide layer on the silicon substrate including the trench oxide layer pattern.
2. The method of claim 1 , wherein the P-well and N-well are formed during an anneal step for forming the gate oxide layer.
3. The method of claim 2 , wherein the forming of the P-type region and N-type region comprises:
forming a buffer oxide layer on the silicon substrate;
forming a first mask pattern to expose a first region of the buffer oxide layer;
forming the P-type region in the silicon substrate by implanting P-type impurities using the first mask pattern as an ion implantation mask;
removing the first mask pattern; forming a second mask pattern to expose a second region of the buffer oxide layer; and
forming the N-type region in the silicon substrate by implanting N-type impurities using the second mask pattern as an ion implantation mask.
4. The method of claim 1 , wherein the forming of the silicon nitride layer pattern and pad oxide layer pattern comprises:
sequentially forming a pad oxide layer and silicon nitride layer on the silicon substrate including the P-type region and N-type region; and
exposing the surface of the silicon substrate by patterning the silicon nitride layer and pad oxide layer.
5. The method of claim 2 , wherein the forming of the layer pattern and pad oxide layer pattern comprises:
sequentially forming a pad oxide layer and silicon nitride layer on a silicon substrate including the P-type region and N-type region; and
exposing the surface of the silicon substrate by patterning the silicon nitride layer and pad oxide layer.