Method of forming a metal interconnection line in a semiconductor device using an FSG layer

1. A method of forming a metal line in a semiconductor device, comprising:

forming a lower metal layer on an insulation layer on a semiconductor substrate;

forming a metal oxide layer on a sidewall of the lower metal layer;

forming a barrier insulation layer covering the lower metal layer and metal oxide layer;

forming a fluorine doped silica glass (FSG) insulation layer on the barrier insulation layer;

forming a via contact that penetrates the FSG insulation layer and the barrier insulation layer so as to directly contacts the lower metal layer without the interposition of a layer between the via contact and sides of the FSG insulation layer; and

forming an upper metal layer electrically connected to the via contact.

2. The method of claim 1 , wherein the forming of the metal oxide layer is performed by an annealing process for the substrate including the lower metal layer, under an oxygen atmosphere.

3. The method of claim 2 , wherein the annealing process is performed at a temperature of 380-415° C. in order to prevent damage to a metal line.

4. The method of claim 1 , wherein the barrier insulation layer is formed as a liner oxide layer.

5. The method of claim 4 , wherein the liner oxide layer is formed by using a CVD method.

6. The method of claim 1 , further comprising forming an undoped silica glass (USG) insulation layer on the fluorine doped silica glass (FSG) insulation layer.

7. The method of claim 1 , wherein the metal layer is formed as an aluminum layer.

8. The method of claim 1 , wherein the metal oxide layer is formed as an aluminum oxide layer.