Flash memory cell and method for manufacturing the same
View Patent ↗An active region and a trench region are formed on a semiconductor substrate. The trench region is filled with a dielectric material to form an isolation layer. Oxide and polysilicon layers are formed on the semiconductor substrate. A second polysilicon layer, a second oxide layer, and a first polysilicon layer are patterned to form a plurality of gate lines. Deep ion implantation in a deep portion of the active region is performed using a self-aligned source mask. The active region and the trench region are exposed through the self-aligned source mask by etching the isolation layer between the plurality of gate lines using the self-aligned source mask to form a common source region. Ions are implanted in the common source region using the self-aligned source mask.
1. A method for manufacturing a flash memory cell, comprising:
forming an active region and a trench region on a semiconductor substrate;
filling the trench region with a dielectric material to form an isolation layer;
forming a first oxide layer, a first polysilicon layer, a second oxide layer, and a second polysilicon layer on the semiconductor substrate;
patterning the second polysilicon layer, the second oxide layer, and the first polysilicon layer to form a plurality of gate lines;
performing deep ion implantation in a deep portion of the active region using a self-aligned source mask;
exposing the active region and the trench region through the self-aligned source mask by etching the isolation layer between the plurality of gate lines using the self-aligned source mask to form a common source region; and
implanting ions in the common source region using the self-aligned source mask.
2. The method according to claim 1 , wherein the active region is a source region.
3. The method according to claim 2 , wherein the implanting ions step comprises implanting ions into surfaces of the source region and the trench region.
4. The method according to claim 3 , wherein an implantation height of the ions in a deep portion of the source region is approximately the same as an implantation height of the ions in the surface of the trench region.
5. The method according to claim 1 , wherein the deep ion implantation uses N-type ions.
6. The method according to claim 5 , wherein the N-type ions are arsenic (As) ions.
7. The method according to claim 6 , wherein the deep ion implantation is performed at a dosage of 5×10 14 -5×10 15 and an implantation energy of 300-500 KeV.
8. The method according to claim 5 , wherein the N-type ions are phosphorous (P) ions.
9. The method according to claim 8 , wherein the deep ion implantation is performed at a dosage of 5×10 14 -5×10 5 and an implantation energy of 150-300 KeV.
10. The method according to claim 1 , wherein the deep ion implantation step is performed at an inclined angle and parallel to a word line.
11. The method according to claim 10 , wherein the inclined angle of the deep ion implantation step is a positive angle for one half of the implantation and is a negative angle for the other half of the implantation.
12. The method according to claim 1 , further comprising forming a plurality of trench lines.
13. The method according to claim 12 , wherein the plurality of trench lines is parallel to a bit line and wherein the plurality of gate lines is parallel to a word line.
14. The method according to claim 1 , wherein the self-aligned source mask exposes a portion of the plurality of gate lines and a gap between adjacent gate lines.