Method of fabricating a floating gate for a nonvolatile memory
View Patent ↗A method of fabricating a gate structure (such as a floating gate) of a nonvolatile (e.g., flash) memory is described. After a polysilicon layer and a mask layer (e.g., silicon nitride) are formed on a semiconductor substrate, the silicon nitride layer is patterned and the polysilicon layer is partially etched. Then, a sidewall spacer is formed on sidewalls of the partially etched polysilicon layer and the patterned mask layer. The partially etched polysilicon layer is then fully etched, maintaining a partially etched shape at its top edge due to the sidewall spacer. The mask layer and the sidewall spacer are removed, to form a floating gate having a near-round edge shape. After full etching, the polysilicon layer may be heat-treated such that its top edge shape may become more rounded, fluent and/or stress- and/or strain-relieving.
1. A method of fabricating a floating gate for a nonvolatile memory, the method comprising:
forming in sequence a tunnel oxide layer, a polysilicon layer, and a first mask layer on a semiconductor substrate having an isolation region;
selectively etching the first mask layer to produce a mask pattern, and partially etching the polysilicon layer exposed through the mask pattern;
forming a sidewall spacer on sidewalls of the partially etched polysilicon layer and the mask pattern;
fully etching the polysilicon layer using both the sidewall spacer and the mask pattern as a mask, whereby the fully etched polysilicon layer has a partially etched shape at its top edge; and
removing the mask pattern and the sidewall spacer such to form a floating gate.
2. The method of claim 1 , further comprising: heat-treating the polysilicon layer after fully etching the polysilicon layer such that the top edge shape of the polysilicon layer changes.
3. The method of claim 1 , wherein fully etching the polysilicon layer comprises a dry etching process.
4. The method of claim 3 , further comprising:
performing a heat treatment process in the presence of oxygen gas, after the dry etching process.
5. The method of claim 1 , wherein forming the sidewall spacer includes depositing a second mask layer and then anisotropically etching the second mask layer.
6. The method of claim 5 , wherein the first mask layer and the second mask layer each comprise silicon nitride.
7. The method of claim 1 , wherein the mask pattern and the sidewall spacer each comprise silicon nitride.
8. The method of claim 7 , wherein removing the mask pattern and the sidewall spacer comprises treating the mask pattern and the sidewall spacer with phosphoric acid.
9. The method of claim 1 , wherein the floating gate imparts less stress and/or strain on an overlying dielectric with the partially etched shape than without and/or has stepped edge shape.
10. A method of fabricating a nonvolatile memory structure, comprising:
selectively etching a first mask layer over a gate layer on a semiconductor substrate to produce a mask pattern;
partially etching the gate layer exposed through the mask pattern;
forming a sidewall spacer on sidewalls of the partially etched gate layer and the mask pattern;
fully etching the gate layer exposed through the sidewall spacer and the mask pattern; and
removing the mask pattern and the sidewall spacer to form the nonvolatile memory structure.
11. The method of claim 10 , wherein the gate layer comprises polysilicon, and the semiconductor substrate has a plurality of isolation regions therein.
12. The method of claim 10 , wherein the fully etched gate layer has a partially etched shape at its top edge.
13. The method of claim 10 , wherein the nonvolatile memory structure comprises a floating gate, and a tunnel oxide layer is between the floating gate and the substrate.
14. The method of claim 13 , wherein the floating gate imparts lower stress and/or strain on an overlying dielectric, and/or has a rounded edge shape.
15. A nonvolatile memory gate structure, comprising:
a semiconductor substrate having a plurality of isolation regions therein;
a tunnel oxide layer thereon; and
a gate layer thereover, having a partially etched step shape exposed at its top edge by removing a mask pattern and a sidewall spacer.
16. The structure of claim 15 , wherein the gate layer comprises a floating gate on the tunnel oxide layer.
17. The structure of claim 16 , wherein the floating gate imparts less stress and/or strain on an overlying dielectric with the partially etched shape than without.
18. The structure of claim 15 , wherein the partially etched shape has a substantially horizontal surface substantially perpendicular to a sidewall of the gate layer, and a substantially vertical surface substantially perpendicular to an uppermost surface of the gate layer.
19. The structure of claim 18 , wherein a height difference between the substantially horizontal surface and the uppermost surface of the gate layer is from about 50% to about 95% of a thickness of the gate layer.
20. The structure of claim 18 , wherein a distance between the substantially vertical surface and a gate layer sidewall closest to an adjacent gate layer sidewall is from about 10% to about 100% of a spacing between the closest gate layer sidewall and the adjacent gate layer sidewall.