Method of fabricating low-power CMOS device
View Patent ↗A low-power CMOS device can be fabricated by forming a shallow trench on a silicon substrate using a gate mask and negative photoresist. This enables an extremely low profile for a junction after completion of lightly doped drain and source/drain implantations. The method includes forming a shallow trench in a silicon substrate.
1. A method of fabricating a low-power CMOS device, comprising:
providing a silicon substrate;
forming forming a shallow trench in the silicon substrate using a gate mask and negative photoresist;
forming a gate oxide layer in the shallow trench of the silicon substrate; forming a gate polysilicon layer on the gate oxide layer;
patterning the gate polysilicon layer and the gate oxide layer using the gate mask to form a gate on the shallow trench;
forming a lightly doped drain layer adjacent to the trench;
oxidizing a sidewall of the gate polysilicon;
forming a source/drain layer under the lightly doped drain layer of the silicon substrate;
forming a silicide layer by self-aligned silicidation;
forming an interlayer dielectric; and
forming a contact hole.
2. The method of claim 1 , wherein the shallow trench is formed by reactive ion etching.
3. The method of claim 1 , further comprising forming the gate oxide layer using a furnace.
4. The method of claim 1 , further comprising forming the gate polysilicon by low-pressure chemical vapor deposition to fabricate a transistor.
5. The method of claim 1 , wherein an implantation depth of the lightly doped drain layer is lowered.
6. The method of claim 1 , wherein an implantation depth of the source/drain layer is lowered.
7. A method of fabricating a low-power CMOS device, comprising:
providing a silicon substrate;
forming a shallow trench in the silicon substrate using a gate mask and negative photoresist, wherein a thickness of the silicon substrate is approximately 50 nm;
depositing a gate oxide layer on the silicon substrate using a furnace;
forming a lightly doped drain layer adjacent to the trench;
forming a gate polysilicon on the gate oxide layer;
patterning the gate oxide layer to form a gate using the gate mask oxidizing a sidewall of the gate polysilicon;
forming a source/drain layer under the lightly doped drain layer of the silicon substrate;
forming a silicide layer by self-aligned silicidation;
forming an interlayer dielectric; and
forming a contact hole.
8. The method of claim 7 , wherein the shallow trench is formed by reactive ion etching.
9. The method of claim 7 , wherein an implantation depth of the lightly doped drain layer is lowered.
10. The method of claim 7 , wherein an implantation depth of the source/drain layer is lowered.