IP Library Granted Patent US 7,507,635
Granted Patent B2
US 7,507,635 · App. 11/318,434 · Granted Mar 24, 2009

CMOS image sensor and method of fabricating the same

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Quick Facts
Patent No.
US 7,507,635
App. No.
11/318,434
Granted
Mar 24, 2009
Kind
B2
Abstract

A CMOS image sensor and method for fabricating the same, wherein the CMOS image sensor has minimized dark current at the boundary area between a photodiode and an isolation layer. The present invention includes a first-conductivity-type doping area formed in the device isolation area of the substrate, the first-conductivity-type doping area surrounding the isolation area and a dielectric layer formed between the isolation layer and the first-conductivity-type doping area, wherein the first-conductivity-type doping area and the dielectric layer are located between the isolation layer and a second-conductivity-type diffusion area.

Claims (17)

1. A method of fabricating a CMOS image sensor, comprising the steps of:

forming a pad oxide layer and a nitride layer sequentially over a first-conductivity-type semiconductor substrate defined by an active area and a device isolation area;

selectively etching the nitride layer to form an opening through which a part of the pad oxide layer is exposed;

forming a first-conductivity-type doping area using the selectively etched nitride layer as a mask;

forming spacers on sidewalls of the opening;

selectively etching the exposed part of the pad oxide layer and underlying substrate using the etched nitride layer and the spacers as a mask to form a trench;

forming a dielectric layer in the trench;

forming an isolation layer on the dielectric layer to fill the trench;

removing the spacers, the nitride layer and the pad oxide layer; and

forming a second-conductivity-type diffusion area in the active area of the substrate in such a way that between the second-conductivity-type diffusion area and the isolation layer is a space corresponding to the first-conductivity-type doping area and the dielectric layer.

2. The method of claim 1 , wherein the step of forming the dielectric layer in the trench comprises a process of thermally oxidizing the substrate including the trench at 800 ˜1150°C.

3. The method of claim 1 , wherein the dielectric layer is formed to have a thickness of 50˜500 Å.

4. The method of claim 1 , wherein the first-conductivity-type doping area is formed by injecting B or BF 2 into the device isolation area of the substrate.

5. The method of claim 1 , the spacers are formed by forming a nitride layer on entire surface of the substrate and carrying out etch-back thereof.

6. The method of claim 1 , wherein the first-conductivity-type substrate comprises:

a high density first-conductivity-type silicon; and

a low density first-conductivity-type epitaxial layer formed on the high density first-conductivity-type silicon.

Assignments (4)
CHANGE OF NAME Recorded Nov 30, 2017
From: DONGBU HITEK CO., LTD.
To: DB HITEK CO., LTD
Reel/Frame 044555/0913 →
MERGER AND CHANGE OF NAME Recorded Nov 29, 2017
From: DONGBU ELECTRONICS CO., LTD.; DONGBU HITEK CO., LTD.
To: DONGBU HITEK CO., LTD.
Reel/Frame 044533/0523 →
CHANGE OF NAME Recorded Jun 15, 2006
From: DONGBUANAM SEMICONDUCTOR INC.
To: DONGBU ELECTRONICS CO., LTD.
Reel/Frame 018176/0351 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 28, 2005
From: HAN, CHANG HUN
To: DONGBUANAM SEMICONDUCTOR, INC.
Reel/Frame 017430/0046 →