IP Library Granted Patent US 7,294,522
Granted Patent B2
US 7,294,522 · App. 11/318,502 · Granted Nov 13, 2007

CMOS image sensor and method for fabricating the same

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Quick Facts
Patent No.
US 7,294,522
App. No.
11/318,502
Granted
Nov 13, 2007
Kind
B2
Abstract

A CMOS image sensor and a method for fabricating the same are disclosed, in which a dead zone and a dark current are simultaneously reduced by selective epitaxial growth. The CMOS image sensor includes a first conductive type semiconductor substrate, a second conductive type impurity ion area, a gate electrode, an insulating film formed on an entire surface of the semiconductor substrate including the gate electrode and excluding the second conductive type impurity ion area, and a silicon epitaxial layer formed on the second conductive type impurity ion area and doped with first conductive type impurity ions.

Claims (13)

1. A method for fabricating a CMOS image sensor comprising:

forming a first conductive type first impurity ion area in an active area of a semiconductor substrate defined by the active area and a field area;

forming a gate electrode on a transistor area of the active area;

forming an insulating film on an entire surface of the semiconductor substrate including the gate electrode;

forming a second conductive type impurity ion area in a photodiode area of the active area;

selectively removing the insulating film on the second conductive type impurity ion area;

growing a silicon epitaxial layer on a surface of the second conductive type impurity ion area; and

forming a first conductive type second impurity ion area in the silicon epitaxial layer.

2. The method of claim 1 , wherein the silicon epitaxial layer is formed on the second conductive type impurity ion area through a selective epitaxial growth process.

3. The method of claim 1 , wherein the step of selectively removing the insulating film further comprises:

leaving the insulating film at sidewalls of the gate electrode so as to isolate the silicon epitaxial layer from the gate electrode through the insulating film.

4. The method of claim 1 , further comprising forming spacers at sidewalls of the gate electrode, and forming a heavily doped second conductive type impurity ion area in the epitaxial layer of the active area at both sides of the gate electrode.

5. The method of claim 4 , wherein the spacers formed at the sidewalls of the gate electrode are adjacent to the silicon epitaxial layer and are formed on the silicon epitaxial layer at the sidewalls of the gate electrode.

Assignments (8)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 27, 2021
From: CAVIUM INTERNATIONAL
To: MARVELL ASIA PTE LTD.
Reel/Frame 057336/0873 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 25, 2021
From: MARVELL TECHNOLOGY CAYMAN I
To: CAVIUM INTERNATIONAL
Reel/Frame 057279/0519 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 23, 2021
From: INPHI CORPORATION
To: MARVELL TECHNOLOGY CAYMAN I
Reel/Frame 056649/0823 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 22, 2017
From: DONGBU HITEK, CO., LTD.
To: INPHI CORPORATION
Reel/Frame 041342/0980 →
CORRECTIVE ASSIGNMENT TO CORRECT REMOVE PATENT NO. 878209 FROM EXHIBIT B PREVIOUSLY RECORDED AT REEL: 034009 FRAME: 0157. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Oct 24, 2014
From: DONGBU HITEK, CO., LTD.
To: INPHI CORPORATION
Reel/Frame 034087/0097 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 15, 2014
From: DONGBU HITEK, CO., LTD.
To: INPHI CORPORATION
Reel/Frame 034009/0157 →
CHANGE OF NAME Recorded Jun 15, 2006
From: DONGBUANAM SEMICONDUCTOR INC.
To: DONGBU ELECTRONICS CO., LTD.
Reel/Frame 018176/0351 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 28, 2005
From: SHIM, HEE SUNG
To: DONGBUANAM SEMICONDUCTOR INC.
Reel/Frame 017383/0566 →