Method of manufacturing semiconductor device having recess gate structure with varying recess width for increased channel length
View Patent ↗A varying-width recess gate structure having a varying-width recess formed in a semiconductor device can sufficiently increase the channel length of the transistor having a gate formed in the varying-width recess, thereby effectively reducing the current leakage and improving the refresh characteristics. In the method of manufacturing the recess gate structure, etching is performed twice or more, so as to form a gate recess having varying width in the substrate, and a gate is formed in the gate recess.
1. A method of manufacturing a semiconductor device having a substrate with an active area defined by an isolation layer, the method comprising:
forming: an oxide layer or an insulation layer; a poly-silicon layer; and a reflection-proof layer on the active area of the semiconductor substrate;
forming a mask pattern defining an expected substrate recess area on the reflection-proof layer;
etching the reflection-proof layer, the poly-silicon layer, and the oxide layer or the insulation layer to expose the expected substrate recess area;
first etching the substrate of the expected recess area to form a first recess having a first recess width and a first recess depth;
removing the mask pattern and the reflection-proof layer;
second etching the substrate at the bottom surface of the first recess by using the etched poly-silicon layer as an etching mask to form a second recess having a second recess width and a second recess depth, wherein the first recess width is wider than the second recess width;
removing the poly-silicon layer and the oxide layer or the insulation layer; and
forming a gate in the first and second recesses.
2. The method as claimed in claim 1 , wherein the first etching is performed by using a mixture solution comprising HF, NH 4 F, HNO 3 , CH 3 COOH, H 2 O 2 , and H 2 O.
3. The method as claimed in claim 2 , wherein the mixture solution contains 1˜50% of CH 3 COOH solution.
4. The method as claimed in claim 2 , wherein the mixture solution contains 1˜50% of HNO 3 solution.
5. The method as claimed in claim 2 , wherein the first etching step is performed at a temperature between 25° C. and 100° C.
6. The method as claimed in claim 1 , wherein the first recess depth is 10˜1000 Å measured from the surface of the substrate.
7. The method as claimed in claim 1 , wherein the second etching step is performed by using a gas containing comprising HBr, N 2 , Ar, Ne, and Cl.
8. The method as claimed in claim 7 , wherein the second etching step further comprises a plasma dry etching in which the etching surface of the first recess is damaged, breaking the crystal lattice on the etching surface.
9. The method as claimed in claim 8 , wherein the plasma dry etching is performed at a temperature between 25° C. and 700° C., at a pressure between 0.1˜100 Torr, by a power between 10 and 2000 Watt, and under a reducing atmosphere.
10. The method as claimed in claim 8 , wherein, in the plasma dry etching, one selected from the group consisting of Ne, He, NH 3 , Kr, Xe and Rn is added as a catalyst gas.
11. The method as claimed in claim 1 , wherein the second recess is formed to have a depth of 300˜3000 Å measured from the surface of the substrate.
12. A method of manufacturing a semiconductor device having a substrate with an active area defined by an isolation layer, the method comprising:
forming an insulation layer on the semiconductor substrate;
forming a mask pattern defining an expected substrate recess area on the insulation layer;
etching the insulation layer by using the mask pattern as an etching mask, to expose the expected substrate recess area;
isotropic etching the substrate of the expected recess area to form a first recess having a first recess width and a first recess depth;
dry etching the substrate at a bottom of the first recess, to form a second recess having a second recess width and a second recess depth, wherein the first recess width is wider than the second recess width; and
forming a gate including poly-silicon layer in both the first and second recesses.
13. The method as claimed in claim 12 , wherein the first isotropic etching is performed by using a mixture solution comprising HF, NH 4 F, HNO 3 , CH 3 COOH, H 2 O 2 and H 2 O.
14. The method as claimed in claim 13 , wherein the mixture solution contains 1˜50% of CH 3 COOH solution.
15. The method as claimed in claim 13 , wherein the mixture solution contains 1˜50% of HNO 3 solution.
16. The method as claimed in claim 12 , wherein the second dry etching is performed by using a gas containing groups of HBr, N 2 , Ar, Ne and Cl.
17. The method as claimed in claim 16 , wherein the second dry etching step further comprising a plasma dry etching in which the etching surface of the first recess is damaged, breaking the crystal lattice on the etching surface.
18. The method as claimed in claim 17 , wherein the plasma dry etching is performed at a temperature between 25° C. and 700° C., at a pressure between 0.1˜100 Torr, by a power between 10 and 2000 Watt, and under a reducing atmosphere.
19. The method as claimed in claim 18 , wherein, in the plasma dry etching, one selected from the group consisting of Ne, He, NH 3 , Kr, Xe and Rn is added as a catalyst gas.