Internal voltage generating apparatus adaptive to temperature change
View Patent ↗An internal voltage generating apparatus adaptive to a temperature change includes a reference voltage circuit including a complementary to absolute temperature (CTAT) type transistor and a proportional to absolute temperature (PTAT) type transistor for generating a first to a third initial reference voltage signals. A buffer circuit for buffering a first, a second and a third initial reference voltage signal is included to generate a first, a second, and a third reference voltage signal in response to enable signals. An internal voltage generating circuit is included to generate an internal voltage signal based on the first, the second and the third reference voltage signal by using an inputted power voltage.
1. An internal voltage generating apparatus of a semiconductor device, comprising:
a reference voltage circuit including a complementary to absolute temperature (CTAT) transistor and a proportional to absolute temperature (PTAT) transistor for generating a first, a second and a third initial reference voltage signal;
a buffer circuit for buffering the first, the second and the third initial reference voltage signal to generate a first, a second and a third reference voltage signal in response to enable signals; and
an internal voltage generating circuit for generating an internal voltage signal based on the first, the second and the third reference voltage signal by using an inputted power voltage.
2. The internal voltage generating apparatus of claim 1 , wherein the first initial reference voltage signal, the second initial reference voltage signal and the third initial reference voltage signal exhibit a negative temperature characteristic, a temperature-independent characteristic and a positive temperature characteristic, respectively.
3. The internal voltage generating apparatus of claim 1 , wherein the first reference voltage signal, the second reference voltage signal and the third reference voltage signal are a CTAT reference voltage signal, a temperature-independent reference voltage signal and a PTAT reference voltage signal, respectively.
4. The internal voltage generating apparatus of claim 1 , wherein the buffer circuit includes:
a first buffer block generating the first reference voltage signal when the first initial reference voltage signal is enabled;
a second buffer block generating the second reference voltage signal when the second initial reference voltage signal is enabled; and
a third buffer block generating the third reference voltage signal when the third initial reference voltage signal is enabled.
5. The internal voltage generating apparatus of claim 4 , wherein the first buffer block, the second buffer block, and the third buffer block operate depending on each enabling state of the enabling signals inputted from an outside.
6. The internal voltage generating apparatus of claim 4 , wherein the internal voltage generating circuit includes:
a comparison block comparing the second reference voltage signal with a reference internal voltage signal and outputting the comparison result;
an internal voltage output block generating the internal voltage signal corresponding to an output value of the comparison block and performing a feedback operation which takes a value of the internal voltage signal as a value of the reference internal voltage signal; and
an enabling block operating the comparison block by a combination of the first reference voltage signal to the third reference voltage signal.
7. The internal voltage generating apparatus of claim 6 , wherein the enabling block includes:
a first transistor receiving the first reference voltage signal through a gate and enabling the comparison block when the first reference voltage signal is inputted;
a second transistor receiving the second reference voltage signal through a gate and enabling the comparison block when the second reference voltage signal is inputted; and
a third transistor receiving the third reference voltage signal through a gate and enabling the comparison block when the third reference voltage signal is inputted.
8. The internal voltage generating apparatus of claim 7 , wherein the first transistor, the second transistor, and the third transistor are connected in parallel.
9. The internal voltage generating apparatus of claim 8 , wherein the first transistor, the second transistor and the third transistor are N-channel metal oxide semiconductor (NMOS) transistors.
10. The internal voltage generating apparatus of claim 7 , wherein the comparison block includes:
a differential input unit receiving and comparing the second reference voltage signal and the reference internal voltage signal with each other; and
a current mirroring unit mirroring a current level corresponding to a comparison value outputted from the differential input unit.
11. The internal voltage generating apparatus of claim 10 , wherein the differential input unit includes NMOS transistors.
12. The internal voltage generating apparatus of claim 11 , wherein the current mirroring unit includes PMOS transistors.
13. The internal voltage generating apparatus of claim 10 , wherein the internal voltage output block includes:
a current supply terminal supplying a certain level of current corresponding to an output value from the comparison block; and
an impedance terminal outputting the internal voltage signal in response to the outputted current from the current supply terminal and performing a feedback operation taking a value corresponding to the internal voltage signal as a value of the reference internal voltage signal.
14. The internal voltage generating apparatus of claim 13 , wherein the impedance terminal includes P-channel metal oxide semiconductor (PMOS) diode dividers for generating a voltage whose level is higher than that of the reference internal voltage signal.
15. The internal voltage generating apparatus of claim 13 , wherein the internal voltage output block further includes capacitors that operate to prevent noise.