Electro-static discharge protection circuit and method for fabricating the same
View Patent ↗An ESD protection circuit using an N-type extended drain silicon controlled rectifier (N-EDSCR) and a method for fabricating the same are provided. An electro-static discharge (ESD) protection circuit includes a substrate, a well formed in the substrate, a drift region having a predetermined portion overlapped with the well, a plurality of first diffusion layers respectively formed in the well and the drift region, a plurality of second diffusion layers respectively formed in the well and the drift region, wherein corresponding first and second diffusion layers in the well are formed separately from each other and those in the drift region are formed adjacent to each other, a source region formed in a manner of surrounding a second conductive type diffusion layer inside the well, and a gate electrode formed on the well between the source and the drift region.
1. An electro-static discharge (ESD) protection circuit, comprising:
a substrate;
a well formed in the substrate;
a drift region having a predetermined portion overlapped with the well;
a plurality of first diffusion layers respectively formed in the well and the drift region;
a plurality of second diffusion layers respectively formed in the well and the drift region, wherein corresponding first and second diffusion layers in the well are formed separately from each other and those in the drift region are formed adjacent to each other;
a source region formed in a manner of surrounding a second diffusion layer inside the well; and
a gate electrode formed on the well between the source and the drift region.
2. The ESD protection circuit of the claim 1 , wherein the first and the second diffusion layers formed in the well and the gate electrode are connected to a first electrode, the first and the second diffusion layers in the drift region are connected to a second electrode, and an ESD stress is coupled to the first and the second electrodes.
3. The ESD protection circuit of the claim 1 , wherein the source region has a different conductive type from the second diffusion layer in the well.
4. The ESD protection circuit of the claim 1 , wherein a dose concentration of the source region is lower than the second diffusion layer inside the well and higher than the drift region.
5. The ESD protection circuit of claim 1 , wherein the second diffusion layer inside the drift region is formed at a predetermined distance from one edge of the drift region adjacent to the gate electrode.
6. The ESD protection circuit of the claim 2 , wherein in case that the ESD stress of a positive voltage is coupled to the first electrode and the ESD stress of a ground voltage is coupled to the second electrode, one of the well and the substrate, and the drift region operate as a forward biased diode.
7. The ESD protection circuit of the claim 1 , wherein a first and a second transistor are coupled with each other to form a silicon controlled rectifier (SCR), the first transistor being formed with the second diffusion layer inside the well, the source region, the well, the drift region and the second diffusion layer inside the drift region, and the second transistor being formed with the first diffusion layer inside the well, the well, the drift region and the first diffusion layer inside the drift region.
8. The ESD protection circuit of the claim 7 , wherein the SCR operates in case that a ground voltage is coupled to a first electrode to which the first and the second diffusion layers inside the well and the gate electrode are connected, and a positive voltage is coupled to a second electrode to which the first and the second diffusion layers inside the drift region are connected.
9. The ESD protection circuit of the claim 1 , further comprising another drift region formed between the second diffusion layer and the source region inside the well in a manner of surrounding said second diffusion layer.
10. The ESD protection circuit of the claim 1 , further comprising a device isolation layer disposed between the first and the second diffusion layers inside the well to isolate the first and the second diffusion layers from each other inside the well.
11. The ESD protection circuit of the claim 10 , further including a diffusion barrier region formed beneath the device isolation layer.
12. The ESD protection circuit of the claim 11 , wherein the source region and the diffusion barrier region are formed simultaneously.
13. An ESD protection circuit, comprising:
a substrate;
a well formed in the substrate;
a drift region formed inside the well;
a plurality of first diffusion layers respectively formed in the well and the drift region;
a plurality of second diffusion layers respectively formed in the well and the drift region, wherein corresponding first and second diffusion layers in the well are formed separately from each other and those in the drift region are formed adjacent to each other;
a source region formed in a manner of surrounding a second diffusion layer inside the well; and
a gate electrode formed on the well between the source region and the drift region.
14. The ESD protection circuit of the claim 13 , wherein the first and the second diffusion layers formed in the well and the gate electrode are connected to a first electrode, the first and the second diffusion layers in the drift region are connected to a second electrode, and an ESD stress is coupled to the first and the second electrodes.
15. The ESD protection circuit of the claim 13 , wherein the source region has a different conductive type from the second diffusion layer in the well.
16. The ESD protection circuit of the claim 13 , wherein a dose concentration of the source region is lower than the second diffusion layer inside the well and higher than the drift region.
17. The ESD protection circuit of claim 13 , wherein the second diffusion layer inside the drift region is formed at a predetermined distance from one edge of the drift region adjacent to the gate electrode.
18. The ESD protection circuit of the claim 14 , wherein in case that the ESD stress of a positive voltage is coupled to the first electrode and the ESD stress of a ground voltage is coupled to the second electrode, one of the well and the substrate, and the drift region operate as a forward biased diode.
19. The ESD protection circuit of the claim 13 , wherein a first and a second transistor are coupled with each other to form a silicon controlled rectifier (SCR), the first transistor being formed with the second diffusion layer inside the well, the source region, the well, the drift region and the second diffusion layer inside the drift region, and the second transistor being formed with the first diffusion layer inside the well, the well, the drift region and the first diffusion layer inside the drift region.
20. The ESD protection circuit of the claim 19 , wherein the SCR operates in case that a ground voltage is coupled to a first electrode to which the first and the second diffusion layers inside the well and the gate electrode are connected, and a positive voltage is coupled to a second electrode to which the first and the second diffusion layers inside the drift region are connected.
21. The ESD protection circuit of the claim 13 , further comprising a device isolation layer disposed between the first and the second diffusion layers inside the well to isolate the first and the second diffusion layers from each other inside the well.
22. The ESD protection circuit of the claim 21 , further including a diffusion barrier region formed beneath the device isolation layer.
23. The ESD protection circuit of the claim 22 , wherein the source region and the diffusion barrier region are formed simultaneously.
24. A method for fabricating an ESD protection circuit, comprising:
providing a substrate in which a well, a device isolation layer and a diffusion barrier region are formed;
forming a source region contacted with one sidewall of the diffusion barrier region and that of the device isolation layer;
forming a drift region having a predetermined portion overlapped with the well;
forming a gate electrode on the well between the source region and the drift region;
forming two first diffusion layers inside the well and the drift region respectively; and
forming two second diffusion layers respectively formed in the well and the drift region, wherein each of the second diffusion layers in the well is formed separately from a corresponding one of the first diffusion layers in the well through the device isolation layer and each of the second diffusion layers is formed adjacent to a corresponding one of the first diffusion layers in the drift region.
25. The method of claim 24 , wherein the source region is formed through an implantation process performed within the same temperature as an implantation process of forming the diffusion barrier region.
26. The method of claim 25 , wherein a dose concentration of the source region is lower than that of the second diffusion layer inside the well and higher than that of the drift region.
27. The ESD protection circuit of the claim 13 , further comprising another drift region formed between the second diffusion layer and the source region inside the well in a manner of surrounding said second diffusion layer.
28. The ESD protection circuit of the claim 11 , wherein the source region is formed before the diffusion barrier region is formed.
29. The ESD protection circuit of the claim 11 , wherein the source region is formed after the diffusion barrier region is formed.
30. The ESD protection circuit of the claim 22 , wherein the source region is formed before the diffusion barrier region is formed.
31. The ESD protection circuit of the claim 22 , wherein the source region is formed after the diffusion barrier region is formed.