Method for forming shallow trench isolation utilizing two filling oxide layers
View Patent ↗A method for forming shallow trench isolation in a semiconductor device. The method includes forming a trench in a predetermined depth on a semiconductor substrate, filling the trench with a first filing oxide, injecting an impurity into a portion of the first filling oxide inside the trench, removing the portion of the first filling oxide by wet etching, and filling the trench with a second filling oxide.
1. A method for forming shallow trench isolation in a semiconductor device, comprising the steps of:
(a) forming a trench of a predetermined depth in a semiconductor substrate;
(b) filling the trench with a first filling oxide, then forming a photoresist mask on the first filling oxide covering an active device area;
(c) implanting an impurity into a central portion of the first filling oxide inside the trench, while the photoresist mask is covering the active device area;
(d) removing the implanted portion of the first filling oxide, by wet etching after implanting the impurity into the central portion of the first filling oxide; and
(e) filling the trench with a second filling oxide.
2. The method of claim 1 , wherein the first filling oxide is a silicon oxide.
3. The method of claim 1 , wherein the second filling oxide is a silicon oxide.
4. The method of claim 2 , wherein the first and second filling oxides are formed by O 3 -TEOS (Tetra Ethyl Ortho Silicate) chemical vapor deposition.
5. The method of claim 2 , wherein the first and second filling oxides are formed by high-density plasma chemical vapor deposition.
6. The method of claim 3 , wherein the first and second filling oxides are formed by O 3 -TEOS (Tetra Ethyl Ortho Silicate) chemical vapor deposition.
7. The method of claim 3 , wherein the first and second filling oxides are formed by high-density plasma chemical vapor deposition.
8. The method of claim 1 , wherein the impurity injected into the portion of the first filling oxide is any one selected from the group consisting of phosphorus (P), boron (B), and argon (Ar).
9. The method of claim 1 , wherein the semiconductor substrate is a silicon substrate.