Metal oxide semiconductor field effect transistor and method of fabricating the same
View Patent ↗There are provided a MOSFET and a method for fabricating the same. The MOSFET includes a semiconductor substrate, a first epitaxial layer in a predetermined location of the semiconductor substrate, a second epitaxial layer doped with high concentration impurity ions on the first epitaxial layer, a gate structure on the second epitaxial layer, and source/drain regions with lightly doped drain (LDD) regions. The first epitaxial layer supplies carriers to the second epitaxial layer so that short channel effects are reduced.
1. A metal oxide semiconductor field effect transistor (MOSFET), comprising:
a semiconductor substrate;
a first epitaxial layer, undoped with impurity ions, at a predetermined location of the semiconductor substrate;
a second epitaxial layer doped with high concentration impurity ions on the first epitaxial layer, wherein an upper surface of the first epitaxial layer contacts a bottom surface of the second epitaxial layer;
a gate structure on the second epitaxial layer; and
source/drain regions with lightly doped drain (LDD) regions in the semiconductor substrate.
2. The MOSFET according to claim 1 , wherein the second epitaxial layer is formed by implanting impurity ions into the semiconductor substrate, and epitaxially growing a surface of the semiconductor substrate.
3. The MOSFET according to claim 1 , wherein the second epitaxial layer acts as a channel region.
4. The MOSFET according to claim 1 , wherein the first epitaxial layer supplies carriers to the second epitaxial layer.
5. The MOSFET according to claim 1 , wherein a ratio of a thickness of the second epitaxial layer to a thickness of the first epitaxial layer is in a range of 1:2 to 1:4.
6. The MOSFET according to claim 1 , wherein a ratio of a total thickness of the first and second epitaxial layers to a critical dimension of the MOSFET is in a range of 1:3 to 1:4.
7. The MOSFET according to claim 1 , wherein a critical dimension of the MOSFET is equal to or greater than a horizontal length of the second epitaxial layer between the source/drain regions, and is equal to or less than a horizontal length of the first epitaxial layer between the source/drain regions.
8. The MOSFET according to claim 1 , wherein the source/drain regions are separated by the first and second epitaxial layers.
9. A metal oxide semiconductor field effect transistor (MOSFET), comprising:
a first epitaxial layer, undoped with impurity ions, in a semiconductor substrate;
a second epitaxial layer doped with impurity ions as a channel in the semiconductor substrate, the second epitaxial layer being over the first epitaxial layer, wherein an upper surface of the first epitaxial layer contacts a bottom surface of the second epitaxial layer;
a gate structure formed on the second epitaxial layer; and
source/drain regions with lightly doped drain (LDD) regions, the source/drain regions being spaced apart by the first and second epitaxial layers.
10. The MOSFET according to claim 9 , wherein the second epitaxial layer is formed by implanting impurity ions into the semiconductor substrate, and epitaxially growing a surface of the semiconductor substrate.
11. The MOSFET according to claim 9 , wherein the first epitaxial layer supplies carriers to the second epitaxial layer.
12. The MOSFET according to claim 9 , wherein a ratio of a thickness of the second epitaxial layer to a thickness of the first epitaxial layer is in a range of 1:2 to 1:4.
13. The MOSFET according to claim 9 , wherein a ratio of a total thickness of the first and second epitaxial layers to a critical dimension of the MOSFET is in a range of 1:3 to 1:4.
14. The MOSFET according to claim 9 , wherein a critical dimension of the MOSFET is equal to or greater than a horizontal length of the second epitaxial layer between the source/drain regions, and is equal to or less than a horizontal length of the first epitaxial layer between the source/drain regions.