IP Library Granted Patent US 7,358,574
Granted Patent B2
US 7,358,574 · App. 11/320,303 · Granted Apr 15, 2008

Semiconductor device having silicide-blocking layer and fabrication method thereof

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Quick Facts
Patent No.
US 7,358,574
App. No.
11/320,303
Granted
Apr 15, 2008
Kind
B2
Abstract

A semiconductor device having a silicide-blocking layer is provided. The device includes a field oxide layer defining an active region, source/drain regions in the active region of a substrate, a gate oxide layer and a gate electrode on the substrate between the source/drain regions, dielectric spacers on sidewalls of the gate electrode, and a silicide layer on both the gate electrode and the source/drain regions. The device also includes the silicide-blocking layer formed over the border between the field oxide layer and the source/drain regions. The silicide-blocking layer covers edges of the source/drain regions, obstructing the extension of the silicide layer.

Claims (18)

1. A semiconductor device comprising:

a silicon substrate having a field oxide layer formed therein to define an active region;

source/drain regions formed in the active region of the substrate;

a gate oxide layer and a gate electrode formed on the substrate between the source/drain regions;

dielectric spacers formed on sidewalls of the gate electrode;

a silicide layer formed on both the gate electrode and the source/drain regions; and

a silicide-blocking layer formed over the borders between the field oxide layer and the source/drain regions, covering edges of the source/drain regions, and obstructing the extension of the silicide layer.

2. The device of claim 1 , wherein the edges of the source/drain regions are higher than edges of the field oxide layer, and the silicide-blocking layer covers the higher edges of the source/drain regions.

3. A method of fabricating a semiconductor device, the method comprising:

forming a field oxide layer in a silicon substrate to define an active region;

forming a gate oxide layer and an overlying gate electrode on the active region of the substrate;

forming dielectric spacers on sidewalls of the gate electrode;

forming source/drain regions in the active region of the substrate;

forming a silicide-blocking layer over the borders between the field oxide layer and the source/drain regions; and

forming a silicide layer on both the gate electrode and the source/drain regions except the blocking layer.

4. The method of claim 3 , wherein the forming of the silicide-blocking layer includes depositing an insulating layer over the substrate and selectively etching the insulating layer.

5. The method of claim 3 , wherein the silicide-blocking layer is formed of silicon oxide or silicon nitride.

6. The method of claim 3 , wherein the silicide-blocking layer is formed of the same material as the dielectric spacers.

Assignments (8)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 27, 2021
From: CAVIUM INTERNATIONAL
To: MARVELL ASIA PTE LTD.
Reel/Frame 057336/0873 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 25, 2021
From: MARVELL TECHNOLOGY CAYMAN I
To: CAVIUM INTERNATIONAL
Reel/Frame 057279/0519 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 23, 2021
From: INPHI CORPORATION
To: MARVELL TECHNOLOGY CAYMAN I
Reel/Frame 056649/0823 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 1, 2017
From: DONGBU HITEK, CO., LTD.
To: INPHI CORPORATION
Reel/Frame 041426/0597 →
CORRECTIVE ASSIGNMENT TO CORRECT REMOVE PATENT NO. 878209 FROM EXHIBIT B PREVIOUSLY RECORDED AT REEL: 034009 FRAME: 0157. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Oct 24, 2014
From: DONGBU HITEK, CO., LTD.
To: INPHI CORPORATION
Reel/Frame 034087/0097 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 15, 2014
From: DONGBU HITEK, CO., LTD.
To: INPHI CORPORATION
Reel/Frame 034009/0157 →
CHANGE OF NAME Recorded Jul 11, 2006
From: DONGBUANAM SEMICONDUCTOR INC.
To: DONGBU ELECTRONICS CO., LTD.
Reel/Frame 018093/0282 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 29, 2005
From: CHOI, CHEE HONG
To: DONGBUANAM SEMICONDUCTOR INC.
Reel/Frame 017429/0795 →