Method for forming a plurality of metal lines in a semiconductor device using dual insulating layer
View Patent ↗A method for forming a plurality of metal lines in a semiconductor device including forming first insulating layer patterns on a semiconductor substrate, the first insulating patterns being spaced from each other; depositing a metal layer on and between the first insulating layer patterns; planarizing the metal layer; patterning the planarized metal layer to form the plurality of metal lines between the first insulating layer patterns; and forming a second insulating layer on and between the metal lines.
1. A method for forming a plurality of metal lines in a semiconductor device, comprising:
forming a first insulating layer on a semiconductor substrate;
patterning the first insulating layer to form a plurality of first insulating layer patterns, said first insulating layer patterns being spaced away from each other;
depositing a metal layer on and between the first insulating layer patterns;
planarizing the metal layer;
patterning the planarized metal layer to form the plurality of metal lines between the adjacent first insulating layer patterns;
forming a second insulating layer on and between the metal lines.
2. The method of claim 1 , wherein the first insulating layer patterns are formed to be lower than the metal lines.
3. The method of claim 2 , wherein a height of the first insulating layer patterns is ⅓ to ⅔ of that of the metal lines.
4. The method of claim 1 , further comprising planarizing the second insulating layer.
5. The method of claim 1 , wherein the metal layer comprises aluminum.
6. The method of claim 1 , wherein the metal layer is deposited by a sputtering process.
7. The method of claim 1 , wherein the second insulating layer is formed by high-density plasma CVD.
8. The method of claim 1 , wherein patterning the planarized metal layer includes patterning by a photolithography and etching processes using a photo mask, said photo mask defines openings over regions in which the first insulating layer patterns are formed.
9. The method of claim 8 , wherein subsequent to patterning the metal layer, an upper surface of each of the first insulating layer patterns is exposed.
10. The method of claim 9 , wherein
the second insulating layer covers an upper side portion and an upper surface of each of the metal lines; and
the second insulating layer covers the upper surface of the first insulating layer patterns.
11. The method of claim 1 , wherein the metal layer covers an entirety of each of the first insulating patterns exposed on the substrate.
12. The method of claim 1 , wherein a thickness of the deposited metal layer is greater than a height of the metal lines.