IP Library Granted Patent US 7,358,563
Granted Patent B2
US 7,358,563 · App. 11/320,467 · Granted Apr 15, 2008

CMOS image sensor and method for fabricating the same

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Quick Facts
Patent No.
US 7,358,563
App. No.
11/320,467
Granted
Apr 15, 2008
Kind
B2
Abstract

A CMOS image sensor and a method for fabricating the same can ensure isolation characteristics using a shallow trench isolation (STI) process and a selective epitaxy method. The CMOS image sensor and method for fabricating the same can also reduce pixel size. The CMOS image sensor includes a semiconductor substrate, a first photodiode, a first epitaxial layer, a second epitaxial layer, a plurality of device isolation layers formed in isolation regions formed at the second epitaxial layer, a second photodiode formed between the device isolation layers, and a third epitaxial layer.

Claims (47)

1. A CMOS image sensor comprising:

a semiconductor substrate including a first epitaxial layer;

a first photodiode formed on the semiconductor substrate including the first epitaxial layer;

a second epitaxial layer formed on the semiconductor substrate including the first photodiode;

a plurality of device isolation layers formed in isolation regions, wherein the isolation regions are formed at the second epitaxial layer;

a second photodiode formed in the second epitaxial layer between the device isolation layers; and

a third epitaxial layer formed on the second epitaxial layer including the second photodiode.

2. The CMOS image sensor according to claim 1 , wherein the third epitaxial layer is selectively grown on the second epitaxial layer except the device isolation layers.

3. The CMOS image sensor according to claim 1 , further comprising:

a first plug formed on the semiconductor substrate for extracting a signal from the first photodiode; and

a second plug formed on the semiconductor substrate for extracting a signal from the second photodiode.

4. The CMOS image sensor according to claim 3 , wherein the first plug is formed from the semiconductor substrate at a side of the first photodiode to the second epitaxial layer and the second plug is formed in the third epitaxial layer.

5. A method of fabricating a CMOS image sensor comprising:

providing a semiconductor substrate including a first epitaxial layer;

forming a first photodiode on the semiconductor substrate including the first epitaxial layer;

forming a second epitaxial layer on the semiconductor substrate including the first photodiode;

forming a first insulating layer on the second epitaxial layer;

selectively etching the second epitaxial layer and the first insulating layer of an isolation region to form a plurality of trenches;

forming a second insulating layer on the first insulating layer including the trenches to fill the first insulating layer in the trenches;

planarizing the second insulating layer to form a plurality of device isolation layers;

removing the first insulating layer;

forming a second photodiode in the second epitaxial layer between the device isolation layers; and

forming a third epitaxial layer on the second epitaxial layer including the second photodiode.

6. The method according to claim 5 , wherein the third epitaxial layer is selectively grown on the second epitaxial layer except the device isolation layers.

7. The method according to claim 5 , further comprising:

forming a first plug on the semiconductor substrate for extracting a signal from the first photodiode; and

forming a second plug on the semiconductor substrate for extracting a signal from the second photodiode.

8. The method according to claim 7 , wherein the first plug is formed from the semiconductor substrate at a side of the first photodiode to the second epitaxial layer and the second plug is formed in the third epitaxial layer.

9. The method according to claim 5 , wherein the step of forming the first photodiode further comprises:

injecting first type impurity ions into an entire surface of the semiconductor substrate including the first epitaxial layer;

depositing a photoresist on the semiconductor substrate;

patterning the photoresist to define an area of the first photodiode;

injecting second type impurity ions into the area of the first photodiode to form the first photodiode; and

removing the photoresist.

10. The method according to claim 5 , wherein the step of forming the second photodiode further comprises:

injecting first type impurity ions into the second epitaxial layer;

depositing a photoresist on the second epitaxial layer;

patterning the photoresist to define an area of the second photodiode;

injecting second type impurity ions into the area of the second photodiode to form the second photodiode; and

removing the photoresist.

11. The method according to claim 5 , further including forming micro lenses.

12. The method according to claim 11 , wherein the step of forming the micro lenses further comprises:

forming light shielding layers on the second insulating layer;

forming a micro lens material on the second insulating layer including the light shielding layers;

etching the micro lens material to planarize the micro lens material;

selectively etching the planarized micro lens material; and

forming the micro lenses by performing a bake process.

Assignments (4)
CHANGE OF NAME Recorded Nov 30, 2017
From: DONGBU HITEK CO., LTD.
To: DB HITEK CO., LTD
Reel/Frame 044555/0913 →
MERGER AND CHANGE OF NAME Recorded Nov 29, 2017
From: DONGBU ELECTRONICS CO., LTD.; DONGBU HITEK CO., LTD.
To: DONGBU HITEK CO., LTD.
Reel/Frame 044533/0523 →
CHANGE OF NAME Recorded Jun 15, 2006
From: DONGBUANAM SEMICONDUCTOR INC.
To: DONGBU ELECTRONICS CO., LTD.
Reel/Frame 018176/0351 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 29, 2005
From: LEE, SANG GI
To: DONGBUANAM SEMICONDUCTOR INC.
Reel/Frame 017431/0347 →