IP Library Patent Application 11320725
Patent Application
App. No. 11/320,725

Method of forming shallow trench isolation in a semiconductor device

Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US None
App. No.
11/320,725
Abstract

An exemplary method of forming a shallow trench isolation layer in a semiconductor device according to an embodiment of the present invention includes depositing a silicon nitride layer as a hard mask layer on a silicon substrate, forming a first moat pattern in the silicon nitride layer by a photolithography process, patterning the silicon nitride layer by a dry etching process using the first moat pattern as an etching mask, forming a shallow trench by dry-etching the substrate that is exposed by the patterned silicon nitride layer, removing the first moat pattern after forming the shallow trench, removing the patterned silicon nitride layer, filling the shallow trench with a gap-fill insulation layer, forming a second moat pattern, removing the gap-fill insulation layer by a dry etching process using the second moat pattern as an etching mask, and removing the second moat pattern.

Claims (20)

1 . A method of forming a shallow trench isolation (STI) layer in a semiconductor device, comprising:

depositing a silicon nitride layer as a hard mask layer on a silicon substrate;

forming a first moat pattern in the silicon nitride layer by a photolithography process;

patterning the silicon nitride layer by a dry etching process using the first moat pattern as an etching mask;

forming a shallow trench by dry-etching the substrate that is exposed by the patterned silicon nitride layer;

removing the first moat pattern after forming the shallow trench;

removing the patterned silicon nitride layer;

filling the shallow trench with a gap-fill insulation layer;

forming a second moat pattern;

removing the gap-fill insulation layer by dry etching process using the second moat pattern as an etching mask; and

removing the second moat pattern so as to form a shallow trench isolation layer.

2 . The method of claim 1 , wherein a depth of the shallow trench is 3000-5000 Å.

3 . The method of claim 1 , wherein a width of the shallow trench is 1500-3000 Å.

4 . The method of claim 1 , further comprising, after filling the shallow trench with a gap-fill insulation layer, planarizing the gap-fill insulation layer by polishing.

5 . The method of claim 4 , wherein, in the planarizing of the gap-fill insulation layer, an etch-stop point is obtained by repeating time-planarizing and monitoring.

6 . The method of claim 4 , wherein the forming a second moat pattern comprises:

coating a photoresist on the planarized gap-fill insulation layer; and

forming a photoresist pattern by exposing and developing the photoresist using a photomask.

7 . The method of claim 1 , wherein, in the patterning the silicon nitride layer by a dry etching process, an etching apparatus using a magnetically enhanced reactive ion etching (MERIE) method is used.

8 . The method of claim 7 , wherein, in the patterning the silicon nitride layer by a dry etching process: an etching gas of CHF3 is flowed at 40-80 sccm, O2 is flowed at 0-20 sccm, and Ar is flowed at 6-120 sccm; a pressure of an etching chamber is maintained at 20 mTorr-70 mTorr; and an RF power is maintained at 200 W-300 W.

Assignments (2)
CHANGE OF NAME Recorded May 23, 2006
From: DONGBU-ANAM SEMICONDUCTOR, INC.
To: DONGBU ELECTRONICS CO., LTD.
Reel/Frame 017663/0468 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 30, 2005
From: AHN, HEUI-GYUN
To: DONGBUANAM SEMICONDUCTOR INC.
Reel/Frame 017430/0211 →