Method and apparatus for diverting void diffusion in integrated circuit conductors
View Patent ↗A method of diverting void diffusion in an integrated circuit includes steps of forming an electrical conductor having a boundary in a first electrically conductive layer of an integrated circuit, forming a via inside the boundary of the electrical conductor in a dielectric layer between the first electrically conductive layer and a second electrically conductive layer of the integrated circuit, and forming a slot between the via and the boundary of the electrical conductor for diverting void diffusion in the electrical conductor away from the via.
1. An apparatus comprising:
an electrical conductor having a boundary formed in a first electrically conductive layer of an integrated circuit;
a via formed inside the boundary of the electrical conductor in a dielectric layer between the first electrically conductive layer and a second electrically conductive layer of the integrated circuit; and
a slot formed inside the boundary of the electrical conductor between the via and the boundary of the electrical conductor for diverting void diffusion in the electrical conductor away from the via.
2. The apparatus of claim 1 further comprising the slot having a shape of a single rectangle.
3. The apparatus of claim 1 further comprising the slot having a shape of an array of rectangles.
4. The apparatus of claim 1 further comprising the slot having a width substantially equal to a width of the via.
5. The apparatus of claim 1 further comprising the slot having a width that is no greater than a width of the via.
6. The apparatus of claim 1 further comprising:
an additional via formed inside the boundary of the electrical conductor between the first electrically conductive layer and a second electrically conductive layer of the integrated circuit; and
an additional slot formed inside the boundary of the electrical conductor between the via and the boundary of the electrical conductor.
7. The apparatus of claim 6 , the additional via further comprising a row or a column of a via array.
8. The apparatus of claim 1 further comprising a side overlap and an end overlap formed between the via and the slot.
9. The apparatus of claim 8 further comprising the side overlap extending about 0.001 microns from the slot to the via and the end overlap extending about 0.055 microns from the slot to the via.
10. The apparatus of claim 1 further comprising a slot array formed adjacent to the boundary of the electrical conductor in an electrically conductive layer of the integrated circuit to relieve a stress gradient in the electrical conductor.
11. The apparatus of claim 1 further comprising the via formed in an elongated rectangular shape.
12. An apparatus comprising:
an electrical conductor having a boundary formed in a first electrically conductive layer of an integrated circuit;
a via formed in a dielectric layer between the first electrically conductive layer and a second electrically conductive layer of the integrated circuit; and
a stress relief void formed in the dielectric layer adjacent to the via for diverting void diffusion in the electrical conductor away from the via.
13. The apparatus of claim 12 further comprising the stress relief void formed in both the dielectric layer and the first electrically conductive layer.