Phase-change-type semiconductor memory device
View Patent ↗A phase-change memory device includes a plurality of bit lines extending in a row direction, a plurality of selection lines extending in a column direction, and an array of memory cells each disposed at one of intersections between the bit lines and selection lines. Each memory cell includes a chalcogenide element and a diode connected in series, and an n-type contact layer underlying the n-type layer of the diode. Adjacent two of memory cells share a common bit-line contact plug connecting the n-type contact layers and the bit line.
1. A semiconductor memory device comprising:
a semiconductor substrate;
a plurality of bit lines overlying said semiconductor substrate and extending parallel to one another;
a plurality of selection lines overlying said semiconductor substrate, extending parallel to one another, and intersecting said bit lines; and
an array of phase-change memory cells each disposed for one of intersections between said bit lines and said selection lines, each of said memory cells being connected between a corresponding one of said bit lines and a corresponding one of said selection lines,
wherein adjacent two of said memory cells share a single bit-line contact plug connected to a corresponding one of said bit lines.
2. The semiconductor memory device according to claim 1 , wherein each of said memory cells includes a phase-change memory element and a diode connected in series with said phase-change memory element, and said diode has a p-n junction configured by an n-type semiconductor layer electrically connected to said bit-line contact plug and a p-type semiconductor layer overlying said n-type semiconductor layer.
3. The semiconductor memory device according to claim 2 , wherein said diodes in said adjacent two of said memory cells configure a pair of diodes formed in a single active region, and both diodes in said pair are isolated from each other by an insulating film covering said shared bit-line contact plug.
4. The semiconductor memory device according to claim 2 , wherein said diodes in said adjacent two of said memory cells configure a pair of diodes formed in separate active regions, and said n-type semiconductor layers in said pair of diodes are connected together by said shared bit-line contact plug.
5. The semiconductor memory device according to claim 2 , wherein said each of shared bit-line contact plugs penetrates said n-type and p-type semiconductor layers while isolated therefrom and is in contact with another n-type semiconductor layer which underlies said n-type semiconductor layer in contact therewith.
6. The semiconductor memory device according to claim 2 , wherein said diodes in said adjacent two of said memory cells comprise a pair of diodes formed in a single active region.
7. The semiconductor memory device according to claim 2 , wherein said diodes in said adjacent two of said memory cells comprise a pair of diodes formed in separate active regions.
8. The semiconductor memory device according to claim 2 , wherein said each of said shared bit-line contact plugs penetrates said n-type and p-type semiconductor layers.
9. The semiconductor memory device according to claim 2 , wherein said each of said shared bit-line contact plugs penetrates said n-type and p-type semiconductor layers while isolated therefrom.
10. The semiconductor memory device according to claim 1 , wherein said bit lines overlie said memory cells and said selection lines.
11. The semiconductor memory device according to claim 1 , wherein said selection lines overlie said bit lines.
12. The semiconductor memory device according to claim 11 , wherein each of said bit lines has a sidewall insulation film, and a contact plug connecting together one of said selection lines and one of said memory cells is deposited in self-alignment with said sidewall insulation film.
13. The semiconductor memory device according to claim 1 , wherein each of said bit lines has a sidewall insulation film, and a contact plug connecting together one of said selection lines and one of said memory cells, and
wherein one of said memory cells is deposited in self-alignment with said sidewall insulation film.
14. The semiconductor memory device according to claim 1 , wherein each of said bit lines has a sidewall insulation film, and a contact plug connecting together one of said selection lines and one of said memory cells.
15. The semiconductor memory device according to claim 1 , wherein said adjacent two of said memory cells are connected to a pair of diodes formed in a single active region.
16. The semiconductor memory device according to claim 1 , wherein said adjacent two of said memory cells are connected to a pair of diodes formed in separate active regions.
17. The semiconductor memory device according to claim 1 , wherein said bit-lines have a sidewall insulation film.