Tileable field-programmable gate array architecture
View Patent ↗An apparatus includes an FPGA, which includes a first FPGA tile including a plurality of FGs, a first, second, and third set of routing conductors, and a plurality of IGs. The FGs are arranged in rows and columns with each FG being configured to receive tertiary and regular input signals, perform a logic operation, and generate regular output signals. The third set of routing conductors is coupled to the first set of output ports of the FGs and configured to receive signals, route signals within the FPGA tile, and provide input signals to the third set of input ports of the FGs. The IGs surround the FGs such that one IG is positioned at each end of each row and column. Each IG is coupled to the third set of routing conductors and configured to transfer signals from the third set of routing conductors to outside the first FPGA tile.
1. A method for providing a routing structure for a field programmable gate array (FPGA) comprising:
providing a first FPGA tile comprising:
providing a plurality of logic components, at least one of said logic components having a first, second and third set of input ports and having a first and second set of output ports;
providing a first set of routing conductors disposed within said first FPGA tile programmably coupled to said first set of output ports of said logic components and configured to receive signals, route signals within said first FPGA tile, and provide said signals to said first set of input ports of said logic components, said first set of routing conductors comprising a plurality of horizontal routing buses and a plurality of vertical routing buses, wherein at least one of said plurality of horizontal routing buses forms an intersection with at least one of said plurality of vertical routing buses at a routing interconnect area;
providing a second set of routing conductors disposed across said first FPGA tile and at least one other FPGA tile, independent of said first set of routing conductors coupled to said second set of output ports and that is configured to receive, select and route signals around said first FPGA tile and within said first FPGA tile, and provide said signals to said second set of input ports of said logic components; and
providing a third set of routing conductors disposed across said first FPGA tile, independent of said first and second set of routing conductors, coupled to at least one of said first output ports of said logic components and configured to receive signals, route signals around said first FPGA tile and within said first FPGA tile, and provide said signals to said third set of input ports of said logic components.
2. The method of claim 1 , wherein said routing interconnect area comprises a programmable interconnect element at said intersection of said at least one of said plurality of horizontal routing buses and said at least one of said plurality of vertical routing buses.
3. The apparatus of claim 2 , wherein said programmable interconnect element comprises a transistor switch and a corresponding memory cell.