Patent Assignment
Reel/Frame 025783/0613
PATENT SECURITY AGREEMENT
Recorded: 2011-02-11
Received: 2011-02-11
Pages: 42
Assignors
ACTEL CORPORATION
Executed: 2011-01-11
MICROSEMI CORPORATION
Executed: 2011-01-11
WHITE ELECTRONIC DESIGNS CORP.
Executed: 2011-01-11
Assignee
MORGAN STANLEY & CO. INCORPORATED
1585 BROADWAY, NEW YORK, NY, 10036, UNITED STATES
Covered Applications
(100)
ENHANCED FIELD PROGRAMMABLE GATE ARRAY
App. No. 12/794,279
→
COAXIAL-TO-MICROSTRIP TRANSITIONS
App. No. 12/788,328
→
METHOD AND APPARATUS FOR STACKED DIE PACKAGE WITH INSULATED WIRE BONDS
App. No. 12/731,420
→
FOUR QUADRANT MOSFET BASED SWITCH
App. No. 12/652,045
→
FULL-BRIDGE AND HALF-BRIDGE COMPATIBLE DRIVER TIMING SCHEDULE FOR DIRECT DRIVE BACKLIGHT SYSTEM
App. No. 12/638,889
→
LESS EXPENSIVE HIGH POWER PLASTIC SURFACE MOUNT PACKAGE
App. No. 12/590,377
→
METHOD AND APPARATUS FOR DRIVING CCFL AT LOW BURST DUTY CYCLE RATES
App. No. 12/610,327
→
FLEXIBLE DIODE PACKAGE AND METHOD OF MANUFACTURING
App. No. 12/589,682
→
SYSTEM AND METHOD FOR IM3 REDUCTION AND CANCELLATION IN AMPLIFIERS
App. No. 12/538,428
→
STRIKING AND OPEN LAMP REGULATION FOR CCFL CONTROLLER
App. No. 12/501,700
→
BALANCING TRANSFORMERS FOR MULTI-LAMP OPERATION
App. No. 12/497,401
→
RF POWER TRANSISTOR PACKAGE
App. No. 12/492,858
→
CCFL CONTROLLER WITH MULTI-FUNCTION TERMINAL
App. No. 12/469,702
→
BATTERY CHARGING AND DISCHARGING BY USING A BI-DIRECTIONAL TRANSISTOR
App. No. 12/434,416
→
LINEARLY REGULATED BATTERY CHARGER
App. No. 12/430,426
→
SPLIT PHASE INVERTERS FOR CCFL BACKLIGHT SYSTEM
App. No. 12/430,715
→
METHOD AND APPARATUS FOR MODIFYING RIGHT HALF-PLANE ZERO IN A CASCADED DC-DC BUCK-BOOST CONVERTER
App. No. 12/405,255
→
DISTRIBUTED AMPLIFIER WITH NEGATIVE FEEDBACK
App. No. 12/391,144
→
ARRAY AND CONTROL METHOD FOR FLASH BASED FPGA CELL
App. No. 12/371,483
→
SINGLE LED STRING LIGHTING
App. No. 12/365,901
→
BALANCING ARRANGEMENT WITH REDUCED AMOUNT OF BALANCING TRANSFORMERS
App. No. 12/363,807
→
DIRECT COUPLED BALANCER DRIVE FOR FLOATING LAMP STRUCTURE
App. No. 12/363,806
→
ADJUSTABLE ROWLOCK
App. No. 12/363,508
→
CLUSTERED FIELD PROGRAMMABLE GATE ARRAY ARCHITECTURE
App. No. 12/362,844
→
SINGLE EVENT TRANSIENT MITIGATION AND MEASUREMENT IN INTEGRATED CIRCUITS
App. No. 12/361,955
→
FIELD PROGRAMMABLE GATE ARRAY ARCHITECTURE HAVING CLOS NETWORK-BASED INPUT INTERCONNECT
App. No. 12/361,835
→
INVERTING FLIP-FLOP FOR USE IN FIELD PROGRAMMABLE GATE ARRAYS
App. No. 12/360,948
→
(N+1) INPUT FLIP-FLOP PACKING WITH LOGIC IN FPGA ARCHITECTURES
App. No. 12/360,971
→
SINGLE EVENT TRANSIENT MITIGATION AND MEASUREMENT IN INTEGRATED CIRCUITS
App. No. 12/352,512
→
PROGRAMMABLE SYSTEM ON A CHIP FOR POWER-SUPPLY VOLTAGE AND CURRENT MONITORING AND CONTROL
App. No. 12/350,419
→
Low Voltage Drop Unidirectional Electronic Valve
App. No. 12/348,002
→
RADIATION TOLERANT SRAM BIT
App. No. 12/345,388
→
PUSH-PULL MEMORY CELL CONFIGURED FOR SIMULTANEOUS PROGRAMMING OF N-CHANNEL AND P-CHANNEL NON-VOLATILE TRANSISTORS
App. No. 12/343,308
→
FINE TUNED MULTIPLE OUTPUT CONVERTER
App. No. 12/340,717
→
PLD PROVIDING SOFT WAKEUP LOGIC
App. No. 12/340,358
→
PROGRAMMABLE LOGIC DEVICE WITH PROGRAMMABLE WAKEUP PINS
App. No. 12/340,440
→
METHOD AND APPARATUS TO CONTROL DISPLAY BRIGHTNESS WITH AMBIENT LIGHT CORRECTION
App. No. 12/336,990
→
PUSH-PULL FPGA CELL
App. No. 12/334,059
→
INTEGRATED CIRCUIT WITH FLEXIBLE PLANAR LEADS
App. No. 12/315,741
→
METHOD AND APPARATUS FOR STACKED DIE PACKAGE WITH INSULATED WIRE BONDS
App. No. 12/269,798
→
EDGE TERMINATION FOR HIGH VOLTAGE SEMICONDUCTOR DEVICE
App. No. 12/206,954
→
CIRCUITS AND METHODS FOR TESTING FPGA ROUTING SWITCHES
App. No. 12/205,656
→
APPARATUS FOR TESTING A PHRASE-LOCKED LOOP IN A BOUNDARY SCAN ENABLED DEVICE
App. No. 12/198,249
→
REDUCED-EDGE RADIATION-TOLERANT NON-VOLATILE TRANSISTOR MEMORY CELLS
App. No. 12/196,978
→
QUADRATIC AND CUBIC COMPENSATION OF SIGMA-DELTA D/A AND A/D CONVERTERS
App. No. 12/187,541
→
Method and Apparatus for Secure Data Storage System
App. No. 12/181,533
→
PROGRAMMABLE SYSTEM ON A CHIP FOR TEMPERATURE MONITORING AND CONTROL
App. No. 12/178,874
→
ESD PROTECTION STRUCTURE FOR I/O PAD SUBJECT TO BOTH POSITIVE AND NEGATIVE VOLTAGES
App. No. 12/179,243
→
SPLIT GATE MEMORY CELL FOR PROGRAMMABLE CIRCUIT DEVICE
App. No. 12/177,680
→
SYSTEM-ON-A-CHIP INTEGRATED CIRCUIT INCLUDING DUAL-FUNCTION ANALOG AND DIGITAL INPUTS
App. No. 12/176,560
→
PROGRAMMABLE DELAY LINE COMPENSATED FOR PROCESS, VOLTAGE, AND TEMPERATURE
App. No. 12/175,399
→
SRAM CELL CONTROLLED BY FLASH MEMORY CELL
App. No. 12/173,117
→
FPGA ARCHITECTURE HAVING TWO-LEVEL CLUSTER INPUT INTERCONNECT SCHEME WITHOUT BANDWIDTH LIMITATION
App. No. 12/173,225
→
CIRCUIT AND METHOD FOR SUPPLYING PROGRAMMING POTENTIAL AT VOLTAGES LARGER THAN BVDSS OF PROGRAMMING TRANSISTORS
App. No. 12/172,675
→
DEGLITCHING CIRCUITS FOR A RADIATION-HARDENED STATIC RANDOM ACCESS MEMORY BASED PROGRAMMABLE ARCHITECTURE
App. No. 12/172,860
→
ARCHITECTURE AND INTERCONNECT SCHEME FOR PROGRAMMABLE LOGIC CIRCUITS
App. No. 12/215,118
→
STAGGERED I/O GROUPS FOR INTEGRATED CIRCUITS
App. No. 12/142,118
→
MIXED SIGNAL SYSTEM-ON-A-CHIP INTEGRATED SIMULTANEOUS MULTIPLE SAMPLE/HOLD CIRCUITS AND EMBEDDED ANALOG COMPARATORS
App. No. 12/139,354
→
REPEATABLE BLOCK PRODUCING A NON-UNIFORM ROUTING ARCHITECTURE IN A FIELD PROGRAMMABLE GATE ARRAY HAVING SEGMENTED TRACKS
App. No. 12/131,258
→
NON-VOLATILE MEMORY ARCHITECTURE FOR PROGRAMMABLE-LOGIC-BASED SYSTEM ON A CHIP
App. No. 12/131,377
→
BLOCK SYMMETRIZATION IN A FIELD PROGRAMMABLE GATE ARRAY
App. No. 12/130,876
→
RADIATION-TOLERANT FLASH-BASED FPGA MEMORY CELLS
App. No. 12/124,661
→
DEDICATED INTERFACE ARCHITECTURE FOR A HYBRID INTEGRATED CIRCUIT
App. No. 12/114,143
→
ENHANCED FIELD PROGRAMMABLE GATE ARRAY
App. No. 12/111,660
→
FIELD-PROGRAMMABLE GATE ARRAY LOW VOLTAGE DIFFERENTIAL SIGNALING DRIVER UTILIZING TWO COMPLIMENTARY OUTPUT BUFFERS
App. No. 12/109,487
→
CLOCK TREE NETWORK IN A FIELD PROGRAMMABLE GATE ARRAY
App. No. 12/105,524
→
LOGIC MODULE INCLUDING VERSATILE ADDER FOR FPGA
App. No. 12/101,589
→
THREE INPUT FIELD PROGRAMMABLE GATE ARRAY LOGIC CIRCUIT CONFIGURABLE AS A THREE INPUT LOOK UP TABLE, A D-LATCH OR A D FLIP- FLOP
App. No. 12/046,160
→
RADIATION TOLERANT SRAM BIT
App. No. 12/045,424
→
COAXIAL-TO-MICROSTRIP TRANSITIONS AND MANUFACTURING METHODS
App. No. 12/038,546
→
BLOCK LEVEL ROUTING ARCHITECTURE IN A FIELD PROGRAMMABLE GATE ARRAY
App. No. 12/034,555
→
INTEGRATED CIRCUIT DEVICE HAVING STATE-SAVING AND INITIALIZATION FEATURE
App. No. 12/028,615
→
HIGH-VOLTAGE DUAL-POLARITY I/O P-WELL PUMP ESD PROTECTION CIRCUIT
App. No. 12/028,692
→
PROGRAMMING METHOD FOR NON-VOLATILE MEMORY AND NON-VOLATILE MEMORY-BASED PROGRAMMABLE LOGIC DEVICE
App. No. 12/024,867
→
PROGRAMMABLE LOGIC DEVICE WITH A MICROCONTROLLER-BASED CONTROL SYSTEM
App. No. 12/023,299
→
ISOLATION SCHEME FOR STATIC AND DYNAMIC FPGA PARTIAL PROGRAMMING
App. No. 12/022,921
→
FAST CARRY LOOKAHEAD CIRCUITS
App. No. 12/022,721
→
RECONFIGURABLE DELTA SIGMA ANALOG-TO-DIGITAL CONVERTER AND CUSTOMIZED DIGITAL FILTERS WITH EMBEDDED FLASH FPGA AND FLASH MEMORY
App. No. 12/022,064
→
FLEXIBLE CARRY SCHEME FOR FIELD PROGRAMMABLE GATE ARRAYS
App. No. 11/962,922
→
NON-VOLATILE TWO-TRANSISTOR PROGRAMMABLE LOGIC CELL AND ARRAY LAYOUT
App. No. 11/962,615
→
NON-VOLATILE MEMORY ARRAY HAVING DRAIN-SIDE SEGMENTATION FOR AN FPGA DEVICE
App. No. 11/961,203
→
BOOST CONVERTER WITH ADAPTIVE COIL PEAK CURRENT
App. No. 11/961,176
→
NON-VOLATILE MEMORY WITH SOURCE-SIDE COLUMN SELECT
App. No. 11/961,134
→
USING A TRIANGULAR WAVEFORM TO SYNCHRONIZE THE OPERATION OF AN ELECTRONIC CIRCUIT
App. No. 11/955,477
→
METHOD FOR PRODUCING SHOCK AND TAMPER RESISTANT MICROELECTRONIC DEVICES
App. No. 11/942,572
→
BALANCING TRANSFORMERS FOR MULTI-LAMP OPERATION
App. No. 11/937,693
→
PROGRAMMABLE SYSTEM ON A CHIP FOR POWER-SUPPLY VOLTAGE AND CURRENT MONITORING AND CONTROL
App. No. 11/932,778
→
INTEGRATED CIRCUIT INCLUDING PROGRAMMABLE LOGIC AND EXTERNAL-DEVICE CHIP-ENABLE OVERRIDE CONTROL
App. No. 11/932,901
→
PROGRAMMABLE SYSTEM ON A CHIP FOR POWER-SUPPLY VOLTAGE AND CURRENT MONITORING AND CONTROL
App. No. 11/932,710
→
CLOCK-GENERATOR ARCHITECTURE FOR A PROGRAMMABLE-LOGIC-BASED SYSTEM ON A CHIP
App. No. 11/932,807
→
PROGRAMMABLE SYSTEM ON A CHIP
App. No. 11/932,462
→
PROGRAMMABLE SYSTEM ON A CHIP FOR POWER-SUPPLY VOLTAGE AND CURRENT MONITORING AND CONTROL
App. No. 11/932,661
→
PROGRAMMABLE SYSTEM ON A CHIP
App. No. 11/931,772
→
NON-VOLATILE LOOK-UP TABLE FOR AN FPGA
App. No. 11/929,287
→
PROGRAMMABLE LOGIC DEVICE ADAPTED TO ENTER A LOW-POWER MODE
App. No. 11/928,428
→
PROGRAMMABLE LOGIC DEVICE ADAPTED TO ENTER A LOW-POWER MODE
App. No. 11/928,445
→
NON-VOLATILE TWO-TRANSISTOR PROGRAMMABLE LOGIC CELL AND ARRAY LAYOUT
App. No. 11/927,265
→
NON-VOLATILE TWO-TRANSISTOR PROGRAMMABLE LOGIC CELL AND ARRAY LAYOUT
App. No. 11/927,282
→
NON-VOLATILE TWO-TRANSISTOR PROGRAMMABLE LOGIC CELL AND ARRAY LAYOUT
App. No. 11/927,237
→
CLOCK-GENERATOR ARCHITECTURE FOR A PROGRAMMABLE-LOGIC-BASED SYSTEM ON A CHIP
App. No. 11/871,741
→