ESD protection structure for I/O pad subject to both positive and negative voltages
View Patent ↗An ESD protection circuit is disclosed for an n-channel MOS transistor formed in an inner p-well of a triple-well process and connected to an I/O pad that may experience both positive and negative voltages according to the present invention. A first switch connects the p-well containing the n-channel MOS transistor to ground if the voltage at the I/O pad is positive and a second switch connects the p-well containing the n-channel MOS transistor to the I/O pad if the voltage at the I/O pad is negative. A third switch connects the gate of the n-channel MOS transistor to the p-well if it is turned off and a fourth switch connects the gate of the n-channel MOS transistor to V cc if it is turned on.
1. An ESD protection circuit for an n-channel MOS transistor formed in an inner p-well of a triple-well structure and connected to an I/O pad that may experience both positive and negative voltages comprising:
a first semiconductor switch connecting the p-well containing the n-channel MOS transistor to ground if the voltage at the I/O pad is positive;
a second semiconductor switch connecting the p-well containing the n-channel MOS transistor to the I/O pad if the voltage at the I/O pad is negative;
a resistor coupled between the gate of the n-channel MOS transistor and the p-well containing the n-channel MOS transistor; and
a third semiconductor switch connecting the gate of the n-channel MOS transistor to V cc to turn the n-channel MOS transistor on.
2. The ESD protection circuit of claim 1 wherein:
the first semiconductor switch is an n-channel MOS transistor having a gate coupled to the I/O pad, a source coupled to ground, and a drain coupled to the p-well containing the MOS transistor to be protected;
the second semiconductor switch is an n-channel MOS transistor having a gate coupled to ground, a source coupled to the I/O pad, and a drain coupled to the p-well containing the MOS transistor to be protected; and
the third semiconductor switch is a first p-channel MOS transistor having a gate coupled to an enable signal, a source coupled to V cc , and a drain coupled to the gate of the MOS transistor to be protected.
3. The ESD protection circuit of claim 1 further including a current-sink circuit coupled to the I/O pad.
4. The ESD protection circuit of claim 1 further including a current-source circuit coupled to the I/O pad.
5. The ESD protection circuit of claim 1 further including:
a current-sink circuit coupled to the I/O pad; and
a current source circuit coupled to the I/O pad.
6. The ESD protection circuit of claim 1 wherein both source and drain of the MOS transistor to be protected are both formed according to at least one ESD design rule.
7. A method for protecting structures coupled to an I/O pad of an integrated circuit including a triple-well structure having an inner p-well containing an n-channel MOS transistor having a drain coupled to the I/O pad, including:
sensing the polarity of an external potential applied to the I/O pad;
coupling the inner p-well to ground if the external potential applied to the I/O pad is positive;
coupling the inner p-well to the I/O pad if the external potential applied to the I/O pad is negative; and
coupling an n-well containing the inner p-well to V cc through a resistor.
8. An ESD protection circuit for an n-channel MOS transistor formed in an inner p-well of a triple-well structure and connected to an I/O pad that may experience both positive and negative voltages comprising:
a first semiconductor switch connecting the p-well containing the n-channel MOS transistor to ground if the voltage at the I/O pad is positive; and
a second semiconductor switch connecting the p-well containing the n-channel MOS transistor to the I/O pad if the voltage at the I/O pad is negative.