Patent Assignment
Reel/Frame 037393/0572
CHANGE OF NAME
Recorded: 2015-12-28
Received: 2015-12-28
Pages: 7
Assignor
ACTEL CORPORATION
Executed: 2012-08-23
Assignee
MICROSEMI SOC CORP.
3870 NORTH STREET, SAN JOSE, CA, 95134, UNITED STATES
Covered Applications
(100)
NON-VOLATILE TWO-TRANSISTOR PROGRAMMABLE LOGIC CELL AND ARRAY LAYOUT
App. No. 13/037,507
→
INVERTING FLIP-FLOP FOR USE IN FIELD PROGRAMMABLE GATE ARRAYS
App. No. 12/879,306
→
CIRCUITS AND METHODS FOR TESTING FPGA ROUTING SWITCHES
App. No. 12/860,004
→
SINGLE EVENT TRANSIENT MITIGATION AND MEASUREMENT IN INTEGRATED CIRCUITS
App. No. 12/828,821
→
PUSH-PULL PROGRAMMABLE LOGIC DEVICE CELL
App. No. 12/828,606
→
FRONT TO BACK RESISTIVE RANDOM ACCESS MEMORY CELLS
App. No. 12/829,311
→
RESISTIVE RAM DEVICES FOR PROGRAMMABLE LOGIC DEVICES
App. No. 12/829,300
→
BACK TO BACK RESISTIVE RANDOM ACCESS MEMORY CELLS
App. No. 12/829,305
→
ISOLATED-NITRIDE-REGION NON-VOLATILE MEMORY CELL AND FABRICATION METHOD
App. No. 12/823,369
→
LOGIC MODULE INCLUDING VERSATILE ADDER FOR FPGA
App. No. 12/823,266
→
ARCHITECTURE AND METHOD FOR COMPENSATING FOR DISPARATE SIGNAL RISE AND FALL TIMES BY USING POLARITY SELECTION TO IMPROVE TIMING AND POWER IN AN INTEGRATED CIRCUIT
App. No. 12/753,247
→
(N+1) INPUT FLIP-FLOP PACKING WITH LOGIC IN FPGA ARCHITECTURES
App. No. 12/717,315
→
PROGRAMMABLE DELAY LINE COMPENSATED FOR PROCESS, VOLTAGE, AND TEMPERATURE
App. No. 12/716,469
→
PROGRAMMABLE LOGIC DEVICE WITH A MICROCONTROLLER-BASED CONTROL SYSTEM
App. No. 12/701,068
→
FLEXIBLE CARRY SCHEME FOR FIELD PROGRAMMABLE GATE ARRAYS
App. No. 12/645,863
→
FLASH-BASED FPGA WITH SECURE REPROGRAMMING
App. No. 12/569,084
→
PROGRAMMABLE SYSTEM ON A CHIP FOR POWER-SUPPLY VOLTAGE AND CURRENT MONITORING AND CONTROL
App. No. 12/555,492
→
NON-VOLATILE TWO-TRANSISTOR PROGRAMMABLE LOGIC CELL AND ARRAY LAYOUT
App. No. 12/417,189
→
ARRAY AND CONTROL METHOD FOR FLASH BASED FPGA CELL
App. No. 12/371,483
→
CLUSTERED FIELD PROGRAMMABLE GATE ARRAY ARCHITECTURE
App. No. 12/362,844
→
SINGLE EVENT TRANSIENT MITIGATION AND MEASUREMENT IN INTEGRATED CIRCUITS
App. No. 12/361,955
→
FIELD PROGRAMMABLE GATE ARRAY ARCHITECTURE HAVING CLOS NETWORK-BASED INPUT INTERCONNECT
App. No. 12/361,835
→
INVERTING FLIP-FLOP FOR USE IN FIELD PROGRAMMABLE GATE ARRAYS
App. No. 12/360,948
→
(N+1) INPUT FLIP-FLOP PACKING WITH LOGIC IN FPGA ARCHITECTURES
App. No. 12/360,971
→
NON-VOLATILE TWO-TRANSISTOR PROGRAMMABLE LOGIC CELL AND ARRAY LAYOUT
App. No. 12/359,481
→
SINGLE EVENT TRANSIENT MITIGATION AND MEASUREMENT IN INTEGRATED CIRCUITS
App. No. 12/352,512
→
PUSH-PULL MEMORY CELL CONFIGURED FOR SIMULTANEOUS PROGRAMMING OF N-CHANNEL AND P-CHANNEL NON-VOLATILE TRANSISTORS
App. No. 12/343,308
→
PLD PROVIDING SOFT WAKEUP LOGIC
App. No. 12/340,358
→
PROGRAMMABLE LOGIC DEVICE WITH PROGRAMMABLE WAKEUP PINS
App. No. 12/340,440
→
PUSH-PULL FPGA CELL
App. No. 12/334,059
→
CIRCUITS AND METHODS FOR TESTING FPGA ROUTING SWITCHES
App. No. 12/205,656
→
REDUCED-EDGE RADIATION-TOLERANT NON-VOLATILE TRANSISTOR MEMORY CELLS
App. No. 12/196,978
→
QUADRATIC AND CUBIC COMPENSATION OF SIGMA-DELTA D/A AND A/D CONVERTERS
App. No. 12/187,541
→
PROGRAMMABLE SYSTEM ON A CHIP FOR TEMPERATURE MONITORING AND CONTROL
App. No. 12/178,874
→
ESD PROTECTION STRUCTURE FOR I/O PAD SUBJECT TO BOTH POSITIVE AND NEGATIVE VOLTAGES
App. No. 12/179,243
→
SPLIT GATE MEMORY CELL FOR PROGRAMMABLE CIRCUIT DEVICE
App. No. 12/177,680
→
SYSTEM-ON-A-CHIP INTEGRATED CIRCUIT INCLUDING DUAL-FUNCTION ANALOG AND DIGITAL INPUTS
App. No. 12/176,560
→
PROGRAMMABLE DELAY LINE COMPENSATED FOR PROCESS, VOLTAGE, AND TEMPERATURE
App. No. 12/175,399
→
SRAM CELL CONTROLLED BY FLASH MEMORY CELL
App. No. 12/173,117
→
FPGA ARCHITECTURE HAVING TWO-LEVEL CLUSTER INPUT INTERCONNECT SCHEME WITHOUT BANDWIDTH LIMITATION
App. No. 12/173,225
→
CIRCUIT AND METHOD FOR SUPPLYING PROGRAMMING POTENTIAL AT VOLTAGES LARGER THAN BVDSS OF PROGRAMMING TRANSISTORS
App. No. 12/172,675
→
STAGGERED I/O GROUPS FOR INTEGRATED CIRCUITS
App. No. 12/142,118
→
MIXED SIGNAL SYSTEM-ON-A-CHIP INTEGRATED SIMULTANEOUS MULTIPLE SAMPLE/HOLD CIRCUITS AND EMBEDDED ANALOG COMPARATORS
App. No. 12/139,354
→
NON-VOLATILE MEMORY ARCHITECTURE FOR PROGRAMMABLE-LOGIC-BASED SYSTEM ON A CHIP
App. No. 12/131,377
→
RADIATION-TOLERANT FLASH-BASED FPGA MEMORY CELLS
App. No. 12/124,661
→
LOGIC MODULE INCLUDING VERSATILE ADDER FOR FPGA
App. No. 12/101,589
→
INTEGRATED CIRCUIT DEVICE HAVING STATE-SAVING AND INITIALIZATION FEATURE
App. No. 12/028,615
→
HIGH-VOLTAGE DUAL-POLARITY I/O P-WELL PUMP ESD PROTECTION CIRCUIT
App. No. 12/028,692
→
PROGRAMMING METHOD FOR NON-VOLATILE MEMORY AND NON-VOLATILE MEMORY-BASED PROGRAMMABLE LOGIC DEVICE
App. No. 12/024,867
→
PROGRAMMABLE LOGIC DEVICE WITH A MICROCONTROLLER-BASED CONTROL SYSTEM
App. No. 12/023,299
→
ISOLATION SCHEME FOR STATIC AND DYNAMIC FPGA PARTIAL PROGRAMMING
App. No. 12/022,921
→
FAST CARRY LOOKAHEAD CIRCUITS
App. No. 12/022,721
→
RECONFIGURABLE DELTA SIGMA ANALOG-TO-DIGITAL CONVERTER AND CUSTOMIZED DIGITAL FILTERS WITH EMBEDDED FLASH FPGA AND FLASH MEMORY
App. No. 12/022,064
→
FLEXIBLE CARRY SCHEME FOR FIELD PROGRAMMABLE GATE ARRAYS
App. No. 11/962,922
→
NON-VOLATILE TWO-TRANSISTOR PROGRAMMABLE LOGIC CELL AND ARRAY LAYOUT
App. No. 11/962,615
→
NON-VOLATILE MEMORY ARRAY HAVING DRAIN-SIDE SEGMENTATION FOR AN FPGA DEVICE
App. No. 11/961,203
→
NON-VOLATILE MEMORY WITH SOURCE-SIDE COLUMN SELECT
App. No. 11/961,134
→
PROGRAMMABLE SYSTEM ON A CHIP FOR POWER-SUPPLY VOLTAGE AND CURRENT MONITORING AND CONTROL
App. No. 11/932,778
→
INTEGRATED CIRCUIT INCLUDING PROGRAMMABLE LOGIC AND EXTERNAL-DEVICE CHIP-ENABLE OVERRIDE CONTROL
App. No. 11/932,901
→
PROGRAMMABLE SYSTEM ON A CHIP FOR POWER-SUPPLY VOLTAGE AND CURRENT MONITORING AND CONTROL
App. No. 11/932,710
→
CLOCK-GENERATOR ARCHITECTURE FOR A PROGRAMMABLE-LOGIC-BASED SYSTEM ON A CHIP
App. No. 11/932,807
→
PROGRAMMABLE SYSTEM ON A CHIP FOR POWER-SUPPLY VOLTAGE AND CURRENT MONITORING AND CONTROL
App. No. 11/932,661
→
NON-VOLATILE LOOK-UP TABLE FOR AN FPGA
App. No. 11/929,287
→
PROGRAMMABLE LOGIC DEVICE ADAPTED TO ENTER A LOW-POWER MODE
App. No. 11/928,428
→
PROGRAMMABLE LOGIC DEVICE ADAPTED TO ENTER A LOW-POWER MODE
App. No. 11/928,445
→
NON-VOLATILE TWO-TRANSISTOR PROGRAMMABLE LOGIC CELL AND ARRAY LAYOUT
App. No. 11/927,265
→
NON-VOLATILE TWO-TRANSISTOR PROGRAMMABLE LOGIC CELL AND ARRAY LAYOUT
App. No. 11/927,282
→
NON-VOLATILE TWO-TRANSISTOR PROGRAMMABLE LOGIC CELL AND ARRAY LAYOUT
App. No. 11/927,237
→
CLOCK-GENERATOR ARCHITECTURE FOR A PROGRAMMABLE-LOGIC-BASED SYSTEM ON A CHIP
App. No. 11/871,741
→
NON-VOLATILE MEMORY CELLS IN A FIELD PROGRAMMABLE GATE ARRAY
App. No. 11/868,694
→
VOLATILE DATA STORAGE IN A NON-VOLATILE MEMORY CELL ARRAY
App. No. 11/861,504
→
NONVOLATILE MEMORY INTEGRATED CIRCUIT HAVING ASSEMBLY BUFFER AND BIT-LINE DRIVER, AND METHOD OF OPERATION THEREOF
App. No. 11/859,073
→
NON-VOLATILE LOOK-UP TABLE FOR AN FPGA
App. No. 11/858,330
→
NON-VOLATILE LOOK-UP TABLE FOR AN FPGA
App. No. 11/858,322
→
NON-VOLATILE LOOK-UP TABLE FOR AN FPGA
App. No. 11/858,341
→
FPGA ARCHITECTURE HAVING TWO-LEVEL CLUSTER INPUT INTERCONNECT SCHEME WITHOUT BANDWIDTH LIMITATION
App. No. 11/855,974
→
ADDRESS TRANSITION DETECTOR FOR FAST FLASH MEMORY DEVICE
App. No. 11/833,833
→
ERROR-DETECTING AND CORRECTING FPGA ARCHITECTURE
App. No. 11/829,335
→
PROGRAMMABLE SYSTEM ON A CHIP FOR TEMPERATURE MONITORING AND CONTROL
App. No. 11/774,676
→
CIRCUIT AND METHOD FOR SUPPLYING PROGRAMMING POTENTIAL AT VOLTAGES LARGER THAN BVDSS OF PROGRAMMING TRANSISTORS
App. No. 11/769,169
→
NON-VOLATILE PROGRAMMABLE MEMORY CELL FOR PROGRAMMABLE LOGIC ARRAY
App. No. 11/762,451
→
NON-VOLATILE TWO-TRANSISTOR PROGRAMMABLE LOGIC CELL AND ARRAY LAYOUT
App. No. 11/750,650
→
SYSTEM FOR SIGNAL ROUTING LINE AGGREGATION IN A FIELD-PROGRAMMABLE GATE ARRAY
App. No. 11/745,134
→
SRAM CELL CONTROLLED BY FLASH MEMORY CELL
App. No. 11/740,458
→
INTEGRATED CIRCUIT WAFER WITH INTER-DIE METAL INTERCONNECT LINES TRAVERSING SCRIBE-LINE BOUNDARIES
App. No. 11/695,992
→
FIELD PROGRAMMABLE GATE ARRAY LONG LINE ROUTING NETWORK
App. No. 11/692,717
→
MIXED SIGNAL SYSTEM-ON-A-CHIP INTEGRATED SIMULTANEOUS MULTIPLE SAMPLE/HOLD CIRCUITS AND EMBEDDED ANALOG COMPARATORS
App. No. 11/612,771
→
METHOD FOR ERASING PROGRAMMABLE INTERCONNECT CELLS FOR FIELD PROGRAMMABLE GATE ARRAYS USING REVERSE BIAS VOLTAGE
App. No. 11/567,625
→
INTEGRATED MULTI-FUNCTION ANALOG CIRCUIT INCLUDING VOLTAGE, CURRENT, AND TEMPERATURE MONITOR AND GATE-DRIVER CIRCUIT BLOCKS
App. No. 11/562,049
→
NON-VOLATILE LOOK-UP TABLE FOR AN FPGA
App. No. 11/551,973
→
SYSTEM-ON-A-CHIP INTEGRATED CIRCUIT INCLUDING DUAL-FUNCTION ANALOG AND DIGITAL INPUTS
App. No. 11/551,857
→
POWER-UP AND POWER-DOWN CIRCUIT FOR SYSTEM-ON-A-CHIP INTEGRATED CIRCUIT
App. No. 11/467,279
→
VOLTAGE-AND TEMPERATURE-COMPENSATED RC OSCILLATOR CIRCUIT
App. No. 11/467,475
→
NON-VOLATILE MEMORY CONFIGURATION SCHEME FOR VOLATILE-MEMORY-BASED PROGRAMMABLE CIRCUITS IN AN FPGA
App. No. 11/465,899
→
MIXED-SIGNAL SYSTEM-ON-A-CHIP ANALOG SIGNAL DIRECT INTERCONNECTION THROUGH PROGRAMMABLE LOGIC CONTROL
App. No. 11/465,530
→
FLASH-BASED FPGA WITH SECURE REPROGRAMMING
App. No. 11/463,846
→
DISAGGREGATED STAR PLATFORM MANAGEMENT BUS ARCHITECTURE SYSTEM
App. No. 11/502,324
→
NON-VOLATILE MEMORY ARCHITECTURE FOR PROGRAMMABLE-LOGIC-BASED SYSTEM ON A CHIP
App. No. 11/460,055
→
CLOCK-GENERATOR ARCHITECTURE FOR A PROGRAMMABLE-LOGIC-BASED SYSTEM ON A CHIP
App. No. 11/427,717
→
INTEGRATED CIRCUIT INCLUDING PROGRAMMABLE LOGIC AND EXTERNAL-DEVICE CHIP-ENABLE OVERRIDE CONTROL
App. No. 11/279,046
→