Nonvolatile memory integrated circuit having assembly buffer and bit-line driver, and method of operation thereof
View Patent ↗An assembly buffer and bitline driver circuit has two inverters cross-coupled to form an assembly buffer. A high-voltage latch is formed from cross-coupled high-voltage inverters. A first low-voltage n-channel MOS transistors is coupled to the high-voltage latch to selectively ground the output of the first high-voltage inverter and a second low-voltage n-channel MOS transistors is coupled to the high-voltage latch to selectively ground the output of the other high-voltage inverter. The gate of the first low-voltage n-channel MOS transistor is coupled to one output of one of the inverters forming the assembly buffer latch and the gate of the second low-voltage n-channel MOS transistor is coupled to the output of the other one of the inverters forming the assembly buffer latch. A pre-load circuit is used to prevent data in an unselected circuit from being disturbed.
1. An assembly buffer and bitline driver circuit including:
a data line;
a column line;
a bit line;
a Y-select line;
two low-voltage inverters cross-coupled to form an assembly buffer latch, the assembly buffer latch having a first output coupled to the column line and a second complementary output;
a first switch coupled between the data line and the column line, the first switch having a control element coupled to the Y-select line;
a second switch coupled between the column line and the bit line, the second switch having a control element coupled to a column select signal line;
two high-voltage inverters cross-coupled to form a bitline driver latch, the bitline driver latch having a first output coupled to the bit line and a second complementary output;
a first low-voltage n-channel MOS data-transfer transistor coupled between the output of the first high-voltage inverter and ground, a gate of the first low-voltage n-channel MOS transistor coupled to the complementary output of the assembly buffer latch; and
a second low-voltage n-channel MOS data-transfer transistor coupled between the output of the second high-voltage inverter and ground, a gate of the second low-voltage n-channel MOS transistor coupled to the output of the assembly buffer latch.
2. The assembly buffer and bitline driver circuit of claim 1 , wherein the first switch is a pass gate.
3. The assembly buffer and bitline driver circuit of claim 1 , wherein the first switch is an n-channel MOS column-select transistor having a gate coupled to the column select line.
4. The assembly buffer and bitline driver circuit of claim 1 , further including a pre-load circuit configured to prevent data in an unselected circuit from being disturbed.
5. The assembly buffer and bitline driver circuit of claim 4 , wherein the preload circuit includes:
a first n-channel MOS transistor having a drain coupled to the complemetary output of the assembly buffer latch, a source, and a gate coupled to a LDABF signal line;
a second n-channel MOS transistor having a drain coupled to the source of the first n-channel MOS transistor, a source coupled to ground, and a gate coupled to the column line; and
a third n-channel MOS transistor having a drain coupled to the output of the assembly buffer, a source coupled to the column line, and a gate coupled to a PRELDABF signal line.
6. The assembly buffer and bitline driver circuit of claim 1 , wherein the first output of the bitline driver latch is coupled to the bit line through an n-channel MOS write-high-voltage transistor having a gate coupled to a write-high-voltage signal line.
7. The assembly buffer and bitline driver circuit of claim 1 , further including:
a first n-channel MOS assembly-buffer-read transistor having a gate coupled to the complementary output of the assembly buffer latch, a source coupled to ground, and a drain; and
a second n-channel MOS assembly-buffer-read transistor having a gate coupled to a read-assembly-buffer signal line, a source coupled to the drain of the first n-channel MOS assembly-buffer-read transistor, and a drain coupled to the column line.