Power-up and power-down circuit for system-on-a-chip integrated circuit
View Patent ↗A power-up and power-down circuit for an integrated circuit includes a voltage regulator set for a first voltage. A first I/O pad is coupled internally to an input to the voltage regulator and to first internal circuits. The second voltage is externally coupled to the first I/O pad. A second I/O pad is coupled internally to an output of the voltage regulator configured to drive the base of an external transistor. A third I/O pad of the integrated circuit is coupled internally to a reference-voltage input of the voltage regulator. A fourth I/O pad is coupled to a feedback input of the voltage regulator. A fifth I/O pad of the integrated circuit is coupled internally to logic circuitry that controls power-up and power down of the integrated circuit from internal signals including internal signals from a real-time clock circuit disposed on the integrated circuit.
1. A power-up and power-down circuit for use on an integrated circuit having circuits using a first power-supply voltage and a second power-supply voltage comprising:
a first I/O pad;
a second I/O pad;
a third I/O pad;
a fourth I/O pad;
a fifth I/O pad coupled to circuits in the integrated circuit that use the second voltage;
a bandgap reference;
a voltage regulator set for the first voltage, having an input coupled to the first I/O pad and to circuits in the integrated circuit that use the second voltage, an output coupled to the second I/O pad, a reference input of the internal voltage regulator coupled to the bandgap reference, a first-voltage feedback input coupled to the third I/O pad, and an enable input;
logic circuitry coupled to the fourth I/O pad and configured to drive the enable input of the voltage regulator in response to logic signals from the fifth I/O pad; and
a transistor having a first terminal coupled to the first I/O pad, a gate coupled to the second I/O pad, and a second terminal coupled to the third I/O pad.
2. The power-up and power-down circuit of claim 1 further including:
a real-time clock powered by the second voltage; and
wherein the logic circuitry is coupled to the real-time clock and the fourth I/O pad, and is configured to drive the enable input of the voltage regulator in response to logic signals from at least one of the real-time clock and the fourth I/O pad.
3. The power-up and power-down circuit of claim 1 further including:
programmable logic; and
wherein the logic circuitry is coupled to the programmable logic and the fourth I/O pad, and is configured to drive the enable input of the voltage regulator in response to logic signals from at least one of the programmable logic and the fourth I/O pad.
4. The power-up and power-down circuit of claim 3 wherein:
the programmable logic is powered by the first voltage.
5. The power-up and power-down circuit of claim 1 wherein:
the transistor is an external NPN transistor connected as an emitter follower with the first terminal the collector, the gate the base, and the second terminal the emitter.
6. The power-up and power-down circuit of claim 5 which further comprises:
a filter capacitor coupled between the second terminal of the transistor and ground.