Architecture and method for compensating for disparate signal rise and fall times by using polarity selection to improve timing and power in an integrated circuit
View Patent ↗A method for reducing delay in an integrated circuit by compensating for differences in rise and fall delay times comprises creating a timing graph; computing minimum delay tuples for nodes in the timing graph; if there is not at least one feasible delay tuple, determining a longest path and computing minimum delay tuples for the longest path; changing polarities on the longest path to reduce delays; updating the timing graph by transferring new polarity and delay values; performing timing analysis to determine a new longest path if the new longest path is shorter than the prior longest path, accepting a resulting polarity selection and computing minimum delay tuples for the longest path; if the new longest path is not shorter than the prior longest path, accepting a resulting polarity selection and implementing changes in a user-program bitstream.
1. A method for reducing delay in an integrated circuit by compensating for differences in rise and fall delay times comprising:
creating a timing graph for a circuit having a set of switching output polarities;
computing minimum delay tuples for nodes in the timing graph;
if there is not at least one feasible delay tuple, determining a longest path and computing minimum delay tuples for the longest path;
changing output polarities on the longest path to create a new set of switching output polarities;
updating the timing graph using the new set of output polarities;
performing timing analysis to determine a new longest path;
if there is not at least one feasible delay tuple:
determining a longest path and computing minimum delay tuples for the longest path;
changing output polarities on the longest path to create a new set of switching output polarities;
updating the timing graph using the new set of output polarities;
performing timing analysis to determine a new longest path;
if the new longest path is shorter than the longest path, accepting the new set of switching output polarities;
if the new longest path is not shorter than the prior longest path, accepting the set of switching output polarities; and
implementing a user-program bitstream using the one of the set of switching output polarities and the set of new switching output polarities that was accepted; and
programming the circuit into a programmable logic device using the user-program bitstream.
2. The method of claim 1 further including:
(a) selecting a tree interconnection network;
(b) identifying all LUTs in the tree interconnection network;
(c) selecting the output polarity of all LUTs in the tree interconnection network so that the maximum delay from primary inputs to primary output in the tree interconnection network is minimized; and
repeating (a) through (c) for all other tree interconnection networks in the circuit.