Non-volatile two-transistor programmable logic cell and array layout
View Patent ↗A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory transistor including spaced-apart source and drain regions is formed within the memory-transistor well. A switch transistor including spaced-apart source and drain regions is formed within the switch-transistor well region. A floating gate is insulated from and self aligned with the source and drain regions of the memory transistor and switch transistor. A control gate is disposed above and aligned to the floating gate and with the source and drain regions of the memory transistor and the switch transistor.
1. An array of non-volatile memory cells including:
a semiconductor body;
at least one memory-transistor well disposed within the semiconductor body;
at least one switch-transistor well disposed within the semiconductor body and electrically isolated from the at least one memory transistor well;
a plurality of memory transistors formed within the at least one memory-transistor well, each including spaced-apart source and drain regions;
a plurality of switch transistors formed within the at least one switch-transistor well region, each associated with one of the memory transistors and including spaced-apart source and drain regions;
a floating gate associated with each memory transistor, each floating gate insulated from and self-aligned with the source and drain regions of the switch transistor with which it is associated;
a control gate associated with each memory transistor, each control gate disposed above and self aligned with its floating gate and with the source and drain regions of the at least one switch transistor with which it is associated.
2. The array of claim 1 , further including at least one additional switch transistor disposed in a switch-transistor well and sharing a floating gate and a control gate with one of the memory transistors.
3. The array of claim 1 wherein:
the semiconductor body is n-type;
the at least one memory-transistor well and the at least one switch transistor well are both p-type wells; and
the memory transistors and the switch transistors are n-channel transistors.
4. The array of claim 3 wherein the semiconductor body is an n-type well disposed in a p-type semiconductor substrate.
5. The array of claim 3 wherein:
the semiconductor body is a n-type well formed in a semiconductor substrate; and
the at least one switch-transistor p-type well is spaced apart from the at least one memory-transistor p-type well and is isolated from the memory transistor p-type well by the n-type well.
6. The array of claim 5 , further including at least one additional switch transistor disposed in a switch-transistor p-type well and sharing a floating gate and a control gate with a memory transistor.
7. The array of claim 1 wherein the at least one memory-transistor well and the at least one switch-transistor well are formed to different depths.
8. The array of claim 1 wherein the at least one memory-transistor well is optimized for memory-transistor characteristics and the at least one switch-transistor well is optimized for switch-transistor characteristics.