Non-volatile memory architecture for programmable-logic-based system on a chip
View Patent ↗A programmable system-on-a-chip integrated circuit device includes a programmable logic block. A digital input/output circuit block is coupled to the programmable logic block. A SRAM block is coupled to the programmable logic block. At least one non-volatile memory block is coupled to the programmable logic block. A JTAG port is coupled to the programmable logic block. An analog circuit block including an analog-to-digital converter may be coupled to the programmable logic block and an analog input/output circuit block may be coupled to the analog circuit block.
1. A programmable system-on-a-chip integrated circuit device comprising:
a programmable logic block;
a digital input/output circuit block coupled to the programmable logic block;
a volatile memory block coupled to the programmable logic block;
a redundancy and error-correction block; and
a non-volatile memory block coupled to the programmable logic block through the redundancy and error-correction block.
2. The programmable system-on-a-chip integrated circuit device of claim 1 , wherein said volatile memory block is an SRAM block.
3. The programmable system-on-a-chip integrated circuit device of claim 1 , further including a JTAG port coupled to the programmable logic block.
4. The programmable system-on-a-chip integrated circuit device of claim 1 , wherein the JTAG port is coupled to the programmable logic block through an encryption/decryption circuit block.
5. The programmable system-on-a-chip integrated circuit device of claim 1 , further including:
an analog circuit block including an analog-to-digital converter coupled to the programmable logic block; and
an analog input/output circuit block coupled to the analog circuit block.
6. The programmable system-on-a-chip integrated circuit device of claim 1 , wherein the non-volatile memory block is coupled to the programmable logic block through a circuit block including data path multiplexers.
7. The programmable system-on-a-chip integrated circuit device of claim 1 , further including a second non-volatile memory block coupled to the programmable logic block.
8. The programmable system-on-a-chip integrated circuit device of claim 1 , wherein a parallel memory interface circuit is programmed into the programmable logic block and coupled to the digital input/output circuit block and the non-volatile memory block.
9. The programmable system-on-a-chip integrated circuit device of claim 8 , wherein the parallel memory interface circuit is coupled to the digital input/output circuit block and the non-volatile memory block through an encryption/decryption circuit block.
10. The programmable system-on-a-chip integrated circuit device of claim 9 , wherein the encryption/decryption circuit block is programmed into the programmable logic block.