Method for erasing programmable interconnect cells for field programmable gate arrays using reverse bias voltage
View Patent ↗A method for erasing a non-volatile memory cell interconnect switch in an FPGA comprised providing an FPGA having a core containing a plurality of non-volatile-memory-cell interconnect switches, each switch formed in a switch well region and coupled to a source/drain of an n-channel transistor formed in a grounded well region separate from the switch well region. A non-volatile memory cell interconnect switch is selected for erasing. The switch well region is disconnected from ground. A VCC potential is applied to the switch well region and to the drain of the n-channel transistor to which it is coupled and an erase potential is applied to the gate of the selected non-volatile memory cell interconnect switch.
1. A method for operating a non-volatile memory switch in an FPGA integrated circuit including a first p-well region coupled to ground; an n-channel MOS transistor disposed in the first p-well region, a second p-well region disposed within an n-well and electrically isolated from the first p-well region, and a non-volatile memory switch disposed in the second p-well region, the non-volatile memory switch having a source/drain region coupled to a drain of the n-channel MOS transistor, a source coupled to the second p-well, and a gate, the method comprising;
coupling the second p-well to ground when the integrated circuit is in an operating mode and to V CC when the integrated circuit is in a mode in which the non-volatile memory switch is to be erased; and
coupling the n-well containing the second p-well to a potential of at least V CC when the integrated circuit is in a mode in which the non-volatile memory switch is to be erased.
2. The method of claim 1 wherein coupling the n-well containing the second p-well to a potential of at least V CC when the integrated circuit is in a mode in which the non-volatile memory switch is to be erased comprises coupling the n-well containing the second p-well to a potential of at least V CC through an inverter having an output coupled to the second p-well and an input coupled to a CORE-OFF control signal.
3. The method of claim 2 further including:
entering a programming mode;
coupling the second p-well to V CC and the gate of the non-volatile memory switch to a negative programming potential when the non-volatile memory switch is to be programmed; and
coupling the second p-well to V CC and the gate of the non-volatile memory switch to a potential that is less negative than the negative programming potential when the non-volatile memory switch is not to be programmed.
4. The method of claim 3 wherein coupling the n-well containing the second p-well to V CC when the integrated circuit is in the programming comprises coupling the n-well containing the second p-well to V CC through an inverter having an output coupled to the second p-well and an input coupled to a CORE-OFF control signal.
5. A method for operating an FPGA integrated circuit including a logic circuit in an FPGA core including an inverter having an n-channel MOS transistor formed in a first p-well that is coupled to ground, the inverter having an output programmably driving a logic-circuit node through an n-channel non-volatile switch formed in a second p-well and coupled to a switchable node, a source of the n-channel MOS transistor in the inverter coupled to the switchable node, the method including:
coupling the switchable node to a node-switching circuit;
operating the node-switching circuit to ground the switchable node during logic circuit operation; and
operating the node-switching circuit to connect the switchable node to V CC during a programming operation and during an erase operation.
6. The method of claim 5 wherein coupling the switchable node to a node-switching circuit comprises coupling the switchable node to a node-switching circuit including an inverter having an input coupled to a node-switching control signal and an output coupled to the switchable node.