Non-volatile two-transistor programmable logic cell and array layout
A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory transistor including spaced-apart source and drain regions is formed within the memory-transistor well. A switch transistor including spaced-apart source and drain regions is formed within the switch-transistor well region. A floating gate is insulated from and self aligned with the source and drain regions of the memory transistor and switch transistor. A control gate is disposed above and aligned to the floating gate and with the source and drain regions of the memory transistor and the switch transistor.
1. An array of non-volatile memory cells including:
a semiconductor body;
a first memory-transistor well disposed within the semiconductor body and having a region of higher dopant concentration at a periphery thereof;
a first switch-transistor well disposed within the semiconductor body to a first side of the first memory-transistor well, the first switch-transistor well having a region of higher dopant concentration at a periphery thereof;
a first isolation region formed in the semiconductor body and surrounding the first memory-transistor well and having a doping concentration different from the semiconductor body;
a first underlying deeper isolation region formed in the semiconductor body beneath the first isolation region and having a different dopant concentration from the semiconductor body and the first isolation region;
a second isolation region formed in the semiconductor body and surrounding the first switch-transistor well and having a doping concentration different from the semiconductor body;
a second underlying deeper isolation region formed in the semiconductor body beneath the second isolation region and having a different dopant concentration from the semiconductor body and the second isolation region;
a first plurality of memory-transistors formed within the first memory-transistor well, each including spaced-apart source and drain regions;
a first plurality of switch-transistors formed within the first switch-transistor well, each associated with one of the first plurality of memory-transistors and including spaced-apart source and drain regions;
a floating gate associated with each memory-transistor in the first plurality of memory transistors, each floating gate insulated from and self-aligned with the source and drain regions of the memory-transistor and the one of the first plurality of switch-transistors with which it is associated; and
a control gate associated with each memory-transistor, each control gate disposed above and self aligned with its floating gate and with the source and drain regions of the memory-transistor and the switch-transistor with which it is associated.
2. The array of non-volatile memory cells of claim 1 wherein the first and second isolation regions and the first and second underlying deeper isolation regions are well regions.
3. The array of non-volatile memory cells of claim 1 that further includes:
a second switch-transistor well disposed within the semiconductor body to a second side of the first memory-transistor well opposite the first side, the second switch-transistor well having a region of higher dopant concentration at a periphery thereof;
a third isolation region formed in the semiconductor body and surrounding the second switch-transistor well and having a doping concentration different from the semiconductor body;
a third underlying deeper isolation region formed in the semiconductor body beneath the third isolation region and having a different dopant concentration from the semiconductor body and the third isolation region; and
a second plurality of memory-transistors formed within the first memory-transistor well and including spaced-apart source and drain regions;
a second plurality of switch-transistors formed within the second switch-transistor well, each associated with one of the second plurality of memory-transistors and including spaced-apart source and drain regions;
a floating gate associated with each memory-transistor in the second plurality of memory transistors, each floating gate insulated from and self-aligned with the source and drain regions of the memory-transistor and the one of the second plurality of switch-transistors with which it is associated;
each control gate is associated with a memory-transistor in the second plurality of memory transistors, each control gate disposed above and self aligned with its floating gate and with the source and drain regions of the memory-transistor in the second plurality of memory transistors and the switch-transistor in the second plurality of switch transistors with which it is associated;
a second isolation well region formed in the semiconductor body between the first memory-transistor well and the second switch-transistor well and having a doping concentration different from the semiconductor body, and
an underlying deeper isolation well region formed in the semiconductor body beneath the second isolation well region and having a different dopant concentration from the semiconductor body and the second isolation well region.
4. The array of non-volatile memory cells of claim 3 wherein the third isolation region and the third underlying deeper isolation region are well regions.
5. The array of non-volatile memory cells of claim 1 wherein:
the first memory transistor well contains four memory-transistors formed within it; and
the first switch transistor well contains four switch-transistors formed within it.
6. The array of non-volatile memory cells of claim 1 wherein:
each of the first plurality of memory-transistors is paired with and formed integrally with another memory-transistor with which it shares a source region; and
each of the first plurality of switch-transistors is paired with and formed integrally with another switch-transistor with which it shares a source region.
7. The array of non-volatile memory cells of claim 1 , wherein:
the memory-transistor well is optimized for memory-transistor characteristics; and
the switch-transistor well is optimized for switch-transistor characteristics.
8. The array of non-volatile memory cells of claim 7 wherein the semiconductor body is an n-type well disposed in a p-type semiconductor substrate.
9. The array of non-volatile memory cells of claim 1 , wherein the memory-transistor well is formed to a different depth than switch-transistor well.
10. The array of non-volatile memory cells of claim 1 wherein:
the semiconductor body is an n-type region;
the first memory-transistor well and the switch-transistor well are all p-type wells;
the first second and third isolation regions and the first second and third underlying deeper isolation regions are n-type regions; and
the memory-transistors and the switch-transistors are all n-channel transistors.