Flexible carry scheme for field programmable gate arrays
View Patent ↗A fast, flexible carry scheme for use in clustered field programmable gate array architectures is described. Each cluster has a cluster carry input node, a cluster carry output node, a cluster carry output circuit having an output coupled to the cluster carry output node, a first input coupled to the cluster carry input node, and a second input and a plurality of logic modules each comprising a logic function generator circuit coupled to a carry circuit. The logic modules are coupled in a series carry arrangement between the cluster carry input node and the second input of the cluster carry output circuit such that the least significant bit of an arithmetic logic circuit can be programmably placed in any of the logic modules.
1. A logic module for a field programmable gate array integrated circuit device including:
a first input node;
a second input node;
a third input node;
a fourth input node;
an output node;
a carry input node;
a carry output node;
a first LUT having a first data input coupled to the first input node, a second data input coupled to the second input node, and a third data input coupled to the third input node, the first LUT further having an output;
a second LUT having a first data input coupled to the first input node, a second data input coupled to the second input node, and a third data input coupled to the third input node, the second LUT further having an output;
a first multiplexer having a first data input coupled to the fourth input node, a second data input coupled to the carry input node, a select input, and a data output;
a second multiplexer having a first data input coupled to the output of the first LUT, a second data input coupled to the output of the second LUT, a select input coupled to the output of the first multiplexer, and a data output coupled to the output node;
a third multiplexer having a first data input coupled to the output of the first LUT, a second data input coupled to a high logic level, a third data input coupled to a low logic level, a set of select inputs, and a data output;
a fourth multiplexer having a first data input coupled to the first input node, a second data input coupled to a high logic level, a third data input coupled to a low logic level, a set of select inputs, and a data output; and
a fifth multiplexer having a first data input coupled to the carry input, a second data input coupled to the output of the fourth multiplexer, a select input coupled to the output of the third multiplexer, and a data output coupled to the carry output.
2. The logic module of claim 1 , further including:
a sixth multiplexer having a plurality of data inputs, a set of select inputs, and a data output coupled to the first input node;
a seventh multiplexer having a plurality of data inputs, a set of select inputs, and a data output coupled to the second input node;
a eighth multiplexer having a plurality of data inputs, a set of select inputs, and a data output coupled to the third input node; and
a ninth multiplexer having a plurality of data inputs, a set of select inputs, and a data output coupled to the fourth input node.
3. The logic module of claim 1 , wherein:
the first LUT is programmed to function as an exclusive-OR gate;
the second LUT is programmed to function as an exclusive OR gate; and
the select input of the first multiplexer is set to a logic level that couples the carry input to its data output.
4. The logic module of claim 3 , wherein the data output of the third multiplexer is coupled to a carry propagate node.
5. The logic module of claim 4 wherein:
the first LUT is programmed to perform a first logic function;
the second LUT is programmed t to perform a first logic function; and
the select input of the first multiplexer is set to a logic level that couples the fourth input node to its data output.
6. The logic module of claim 5 , further including:
a sixth multiplexer having a plurality of data inputs, a set of select inputs, and a data output coupled to the first input node;
a seventh multiplexer having a plurality of data inputs, a set of select inputs, and a data output coupled to the second input node;
a eighth multiplexer having a plurality of data inputs, a set of select inputs, and a data output coupled to the third input node; and
a ninth multiplexer having a plurality of data inputs, a set of select inputs, and a data output coupled to the fourth input node.
7. The logic module of claim 6 wherein:
the set of select inputs of the third multiplexer are set to logic levels that couple a selected one of the high logic level and the low logic level to the data output of the third multiplexer; and
the set of select inputs of the fourth multiplexer are set to logic levels that couple a selected one of the high logic level and the low logic level to the data output of the fourth multiplexer.
8. The logic module of claim 7 wherein the set of select inputs of the third multiplexer are set to logic levels that couple the low logic level to the data output of the third multiplexer.