Integrated circuit including programmable logic and external-device chip-enable override control
View Patent ↗An integrated circuit device includes a programmable logic block, a monitoring input, a condition-sensing circuit coupled to the monitoring input and configured to generate a condition-sensed signal at an output in response to sensing a condition at the monitoring input, a first digital input, a first digital output, and a gating circuit configured in the programmable logic block and coupled between the first digital input and the first digital output. The gating circuit has a gating input coupled to the condition-sensing circuit and generates an output. The output is related to an input state of the first digital input in the absence of the condition-sensed signal and assumes an override state in the presence of the condition-sensed signal.
1. A programmable system-on-a-chip integrated circuit device comprising:
a programmable logic block
a digital input/output circuit block;
a non-volatile memory block;
an analog circuit block including an analog-to-digital converter, at least one temperature-sensing circuit coupled to an I/O pad, the temperature-sensing circuit including a programmable voltage prescaling circuit;
an analog input/output circuit block;
a clock generator circuit and distribution block including at least one RC oscillator, a crystal oscillator circuit coupled to I/O pads for coupling to an external crystal, at least one phase locked loop circuit, at least one I/O pad for coupling to an external clock source; and
a programmable interconnect architecture including programmable elements and interconnect conductors, ones of said programmable elements coupled to said programmable logic block, said non-volatile memory block, said analog circuit block, said analog input/output circuit block, said digital input/output circuit block, and to said interconnect conductors, such that inputs and outputs of said programmable logic block, said non-volatile memory block, said analog circuit block, said analog input/output circuit block, and said digital input/output circuit block can be programmably coupled to one another.
2. The programmable system-on-a-chip integrated circuit device of claim 1 further including a static random-access memory block and wherein said programmable interconnect architecture is coupled to said static random-access memory block.
3. The programmable system-on-a-chip integrated circuit device of claim 2 wherein said static random-access memory block is configured into at least two sub-blocks.
4. The programmable system-on-a-chip integrated circuit device of claim 1 further including a microcontroller block and a static random-access memory block and wherein said programmable interconnect architecture is coupled to said microcontroller block and said static random-access memory block.
5. The programmable system-on-a-chip integrated circuit device of claim 4 wherein said static random-access memory block is configured into at least two sub-blocks.
6. The programmable system-on-a-chip integrated circuit device of claim 1 further including a microprocessor block and a static random-access memory block and wherein said programmable interconnect architecture is coupled to said microprocessor block and said static random-access memory block.
7. The programmable system-on-a-chip integrated circuit device of claim 6 wherein said static random-access memory block is configured into at least two sub-blocks.
8. The programmable system-on-a-chip integrated circuit device of claim 1 wherein said non-volatile memory block comprises flash memory.
9. The programmable system-on-a-chip integrated circuit device of claim 1 further including a digital input circuit coupled to said I/O pad.
10. The programmable system-on-a-chip integrated circuit device of claim 1 wherein said analog circuit block further includes at least one voltage-sensing circuit coupled to an I/O pad.
11. The programmable system-on-a-chip integrated circuit device of claim 10 wherein said at least one voltage-sensing circuit includes a programmable voltage prescaling circuit.
12. The programmable system-on-a-chip integrated circuit device of claim 10 further including a digital input circuit coupled to said I/O pad.
13. The programmable system-on-a-chip integrated circuit device of claim 1 wherein said analog circuit block further includes at least one current-sensing circuit coupled to a first I/O pad and a second I/O pad.
14. The programmable system-on-a-chip integrated circuit device of claim 13 wherein said at least one current-sensing circuit includes a programmable voltage prescaling circuit.
15. The programmable system-on-a-chip integrated circuit device of claim 13 further including a digital input circuit coupled to at least one of said first and second I/O pads.
16. The programmable system-on-a-chip integrated circuit device of claim 1 wherein said analog circuit block further includes at least one programmable MOSFET gate-drive circuit coupled to an I/O pad.
17. The programmable system-on-a-chip integrated circuit device of claim 1 wherein said analog circuit block further includes:
at least one MOSFET gate-drive circuit coupled to a first I/O pad,
at least one voltage-sensing circuit coupled to a second I/O pad;
at least one current-sensing circuit coupled to said second I/O pad and a third I/O pad; and
at least one temperature-sensing circuit coupled to a fourth I/O pad.
18. The programmable system-on-a-chip integrated circuit device of claim 17 further including a digital input circuit coupled to one of said second, third, and fourth I/O pads.
19. The programmable system-on-a-chip integrated circuit device of claim 1 wherein said non-volatile memory block has a first segment that may be programmably connected to a user-configured circuit and a second segment that may not be programmably connected to a user-configured circuit.
20. The programmable system-on-a-chip integrated circuit device of claim 1 further including a bandgap reference circuit.
21. The programmable system-on-a-chip integrated circuit device of claim 1 further including a glitchless clock multiplexer coupled between at least two of the at least one RC oscillator, the crystal oscillator circuit coupled to I/O pads for coupling to an external crystal, the at least one phase locked loop circuit, and the at least one I/O pad for coupling to an external clock source.