(N+1) input flip-flop packing with logic in FPGA architectures
View Patent ↗A logic module and flip-flop includes input multiplexers having data inputs coupled to routing resources. A clock multiplexer has inputs coupled to clock resources, and an output. An input-select multiplexer has a first input coupled to the output of an input multiplexer. A flip-flop has a clock input coupled to the output of the clock multiplexer, and a data output coupled to an input of the input-select multiplexer. A logic module has data inputs coupled to the output of the input select multiplexers. A flip-flop multiplexer is coupled to the data input of the flip-flop, and has inputs input coupled to the output of the first input multiplexer, the data output of the logic module, and a third input coupled to routing resources.
1. A logic module and flip-flop arrangement comprising:
a first input multiplexer having a plurality of data inputs coupled to routing resources, and an output;
second through nth input multiplexers, each having a plurality of data inputs coupled to routing resources, and an output;
a clock multiplexer having a plurality of inputs coupled to clock resources, and an output;
an input-select multiplexer having a plurality of inputs and an output, a first input of the input-select multiplexer coupled to the output of the first input multiplexer;
a flip-flop having a clock input coupled to the output of the clock multiplexer, a data output coupled to a second input of the input-select multiplexer, and a data input;
a logic module having a plurality of data inputs and an output, one data input of the logic module coupled to the output of the input select multiplexer, the other data inputs of the logic module each coupled to the output of a different one of the second through nth input multiplexers; and
a flip-flop/routing multiplexer having an output coupled to the data input of the flip-flop, a first input coupled to the output of the first input multiplexer, a second input coupled to the data output of the logic module, and at least one input coupled to routing resources.
2. The logic module and flip-flop arrangement of claim 1 wherein the second through nth input multiplexers comprise second through fourth input multiplexers.
3. The logic module and flip-flop arrangement of claim 1 wherein the at least one input of the flip-flop/routing multiplexer coupled to routing resources comprises a third input.
4. The logic module and flip-flop arrangement of claim 1 wherein the flip-flop/routing multiplexer further includes:
a fourth input coupled to routing resources; and
a fifth input coupled to routing resources.
5. The logic module and flip-flop arrangement of claim 4 wherein:
the logic module further includes a sum output, a carry-in input, and a carry-out output;
the flip-flop/routing multiplexer further includes a sixth input coupled to the sum output of the logic module.
6. The logic module and flip-flop arrangement of claim 1 wherein:
the output of the logic module forms a first output; and
the output of the flip flop forms a second output.
7. The logic module and flip-flop arrangement of claim 4 wherein:
the output of the logic module forms a first output;
the output of the flip flop forms a second output; and
the sum output of the logic module forms a third output.