Volatile data storage in a non-volatile memory cell array
View Patent ↗A method for storing data on nodes in memory cells of a non-volatile memory cell array including steps of setting non-volatile devices of the non-volatile memory cell array to a desired state, biasing pull-up devices and non-volatile devices in a first set of rows of the non-volatile memory cell array to an off state, loading data onto column lines of the non-volatile memory cell array and biasing non-volatile devices in a second set of rows in the memory cells of the non-volatile memory cell array to store data from the column lines on the nodes in the memory cells of the non-volatile memory cell array.
1. An integrated circuit device capable of storing volatile data on common nodes in memory cells of a non-volatile memory cell array comprising:
a non-volatile memory cell array comprising:
column lines;
row lines; and
a plurality of memory cells arranged in rows and columns and coupled to the row lines and the column lines, each memory cell comprising a non-volatile device and a pull-up device connected at a common node;
a means for setting the non-volatile devices of each of the memory cells to a desired state;
a means for loading volatile data onto column lines of the non-volatile memory cell array;
a means for biasing non-volatile devices in the memory cells of the non-volatile memory cell array to store volatile data from said column lines on the common nodes in the memory cells of the non-volatile memory cell array; and
a means for biasing pull-up devices and non-volatile devices in a first set of rows of the non-volatile memory cell array to an off state;
wherein said means for biasing non-volatile devices in the memory cells of the non-volatile memory cell array is directed towards a second set of rows of the non-volatile memory cell array.
2. The integrated circuit device in claim 1 wherein:
said means for setting non-volatile devices of the non-volatile memory cell array to a desired state comprises a means for erasing each of said non-volatile devices in the non-volatile memory cell array.
3. The integrated circuit device in claim 1 further comprising:
a means for testing for the common nodes in the memory cells of the non-volatile memory cell array that cannot store charge as desired.
4. The integrated circuit device in claim 3 further comprising:
a means for storing the location of a row having a common node that cannot store charge as desired as determined in said testing step.
5. The integrated circuit device in claim 1 wherein:
said means for setting comprises a means for erasing each of said non-volatile devices in the non-volatile memory cell array.
6. The integrated circuit device in claim 1 further comprising:
a means for refreshing said volatile data from said column lines stored on the common nodes in the memory cells of the non-volatile memory cell array as desired.
7. The integrated circuit device in claim 3 further comprising:
a means for storing the location of a row having a common node that cannot store charge as desired as determined in said testing step.
8. An integrated circuit device capable of storing volatile data on common nodes in memory cells of a non-volatile memory cell array comprising:
a non-volatile memory cell array comprising:
column lines;
row lines; and
a plurality of memory cells arranged in rows and columns and coupled to the row lines and the column lines, each memory cell comprising a non-volatile device and a pull-up device connected at a common node;
a means for setting non-volatile devices of the non-volatile memory cell array to a desired state;
a means for loading volatile data onto column lines of the non-volatile memory cell array;
a means for biasing pull-up devices and non-volatile devices in the memory cells of the non-volatile memory cell array to store volatile data from said column lines on the common nodes in the memory cells of the non-volatile memory cell array; and
a means for biasing pull-up devices and non-volatile devices in a first set of rows of the non-volatile memory cell array to an off state; and
wherein said means for biasing pull-up devices and non-volatile devices in the memory cells of the non-volatile memory cell array is directed towards a second set of rows of the non-volatile memory cell array.
9. The integrated circuit device in claim 8 wherein:
said means for setting comprises a means for erasing each of said non-volatile devices in the non-volatile memory cell array.
10. The integrated circuit device in claim 8 further comprising:
a means for testing for the common nodes in the memory cells of the non-volatile memory cell array that cannot store charge as desired.
11. The integrated circuit device in claim 10 further comprising:
a means for storing a location of a row having a common node that cannot store charge as desired as determined in said means for testing.
12. The integrated circuit device in claim 8 further comprising:
a means for refreshing said volatile data from said column lines stored on the common nodes in the memory cells of the non-volatile memory cell array as desired.
13. An integrated circuit device capable of storing volatile data on common nodes in memory cells of a non-volatile memory cell array comprising:
a non-volatile memory cell array comprising:
column lines;
row lines; and
a plurality of memory cells arranged in rows and columns and coupled to the row lines and the column lines, each memory cell comprising a non-volatile device and a pull-up device connected at a common node;
a means for setting non-volatile devices of the non-volatile memory cell array to a desired state;
a means for loading volatile data onto column lines of the non-volatile memory cell array; and
a means for biasing pull-up devices in the memory cells of the non-volatile memory cell array to store volatile data from said column lines on the common nodes in the memory cells of the non-volatile memory cell array and;
a means for biasing pull-up devices and non-volatile devices in a first set of rows of the non-volatile memory cell array to an off state;
wherein said means for biasing pull-up devices in the memory cells of the non-volatile memory cell array is directed towards a second set of rows of the non-volatile memory cell array.
14. The integrated circuit device in claim 13 wherein:
said column lines are a single global column line.
15. The integrated circuit device in claim 13 wherein:
said means for setting comprises a means for erasing each of said non-volatile devices in the non-volatile memory cell array.
16. The integrated circuit device in claim 13 further comprising:
a means for testing for common nodes in the memory cells of the non-volatile memory cell array that cannot store charge as desired.
17. The integrated circuit device in claim 16 further comprising:
a means for storing a location of a row having a common node that cannot store charge as desired as determined in said means for testing.
18. The integrated circuit device in claim 13 further comprising:
a means for refreshing said volatile data from said column lines stored on the common nodes in the memory cells of the non-volatile memory cell array as desired.
19. The integrated circuit device in claim 13 wherein:
said column lines are a single global column line.