Integrated circuit including programmable logic and external-device chip-enable override control
View Patent ↗An integrated circuit device includes a programmable logic block, a monitoring input, a condition-sensing circuit coupled to the monitoring input and configured to generate a condition-sensed signal at an output in response to sensing a condition at the monitoring input, a first digital input, a first digital output, and a gating circuit configured in the programmable logic block and coupled between the first digital input and the first digital output. The gating circuit has a gating input coupled to the condition-sensing circuit and generates an output. The output is related to an input state of the first digital input in the absence of the condition-sensed signal and assumes an override state in the presence of the condition-sensed signal.
1. A method for using a programmable system-on-a-chip including digital and analog circuits to send signals to off-chip integrated circuits in an electronic system comprising:
performing a power-up sequence in the system-on-a-chip including:
sensing that power supply voltage is ramping up;
determining that a band-gap circuit in the system-on-a-chip is outputting correct reference voltage;
determining that a first voltage regulator circuit in the system-on-a-chip is outputting correct reference voltage;
determining that an FPGA circuit in the system-on-a-chip is functioning;
determining that a non-volatile memory circuit in the system-on-a-chip is functioning;
determining that a second voltage regulator circuit in the system-on-a-chip is outputting correct reference voltage;
determining that a reference voltage to an analog-to-digital converter circuit in the system-on-a-chip is outputting correct reference voltage;
calibrating the analog-to-digital converter circuit;
initializing and configuring a state machine in the system-on-a-chip; and
monitoring at least one condition of the electronic system.
2. The method of claim 1 wherein determining that the FPGA circuit in the system-on-a-chip is functioning comprises:
determining that the FPGA circuit has become active; and
outputting a signal indicating that the FPGA circuit has become active.
3. The method of claim 1 wherein determining that the non-volatile memory circuit in the system-on-a-chip is functioning comprises:
determining that the non-volatile memory circuit has become active; and
outputting a signal indicating that the non-volatile memory circuit has become active.
4. The method of claim 1 wherein monitoring at least one condition of the electronic system comprises:
sampling a condition of the electronic system to create a condition value;
converting the condition value to a digital condition value;
comparing the digital condition value to a predetermined threshold; and
sending a signal to at least one off-chip integrated circuit if the digital condition value exceeds the predetermined threshold.
5. The method of claim 4 wherein sampling a condition of the electronic system to create a condition value comprises:
sampling a voltage powering a circuit external to the system-on-a-chip;
creating a first condition value if the voltage is within a predetermined specification;
creating a second condition value if the voltage is not within the predetermined specification;
enabling a drive signal to the circuit external to the system-on-a-chip in response to the first condition value; and
disabling the drive signal to the circuit external to the system-on-a-chip in response to the second condition value.
6. The method of claim 5 further comprising:
continuing to sample the voltage powering the circuit external to the system-on-a-chip after disabling the drive signal to the circuit external to the system-on-a-chip in response to the second condition value;
enabling the drive signal to the circuit external to the system-on-a-chip in response to recurrence of the first condition value.
7. The method of claim 6 wherein enabling the drive signal to the circuit external to the system-on-a-chip in response to recurrence of the first condition value comprises enabling the drive signal only after the first condition value has recurred for a predetermined time.
8. The method of claim 5 wherein:
sampling a voltage powering a circuit external to the system-on-a-chip comprises sampling a voltage supplied to an external MOSFET;
enabling a drive signal to the circuit external to the system-on-a-chip in response to the first condition value comprises supplying a voltage to the gate of the external MOSFET sufficient to turn it on; and
disabling the drive signal to the circuit external to the system-on-a-chip in response to the second condition value comprises supplying a voltage to the gate of the external MOSFET sufficient to turn it off.
9. The method of claim 5 further including disabling the drive signal to the circuit external to the system-on-a-chip in response to an external reset signal applied to the system-on-a-chip.
10. The method of claim 9 further including providing a reset-out signal from the system-on-a-chip in response to the external reset signal applied to the system-on-a-chip.