Non-volatile two-transistor programmable logic cell and array layout
View Patent ↗A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory transistor including spaced-apart source and drain regions is formed within the memory-transistor well. A switch transistor including spaced-apart source and drain regions is formed within the switch-transistor well region. A floating gate is insulated from and self aligned with the source and drain regions of the memory transistor and switch transistor. A control gate is disposed above and aligned to the floating gate and with the source and drain regions of the memory transistor and the switch transistor.
1. A non-volatile memory cell including:
a semiconductor body;
a first memory-transistor well disposed within the semiconductor body;
a first memory transistor formed within the first memory-transistor well and including spaced-apart source and drain regions;
a first switch-transistor well disposed within the semiconductor body to a first side of the first memory-transistor well and electrically isolated from the first memory-transistor well;
a first switch transistor formed within the first switch-transistor well and including spaced-apart source and drain regions;
a second switch transistor formed within the first switch-transistor well and including spaced-apart source and drain regions;
a first floating gate insulated from and self aligned with the source and drain regions of the first memory transistor and the first and second switch transistor; and
a first control gate disposed above and self aligned with respect to the first floating gate and with the source and drain regions of the first memory transistor and the first and second switch transistors.
2. The non-volatile memory cell of claim 1 , wherein:
the first memory-transistor well is optimized for memory-transistor characteristics and
the first switch-transistor well is optimized for switch-transistor characteristics.
3. The non-volatile memory cell of claim 1 , wherein the memory-transistor wells and the switch-transistor wells are formed to different depths.
4. The non-volatile memory cell of claim 1 wherein:
the semiconductor body is n-type;
the first memory-transistor well and the first switch-transistor well are all p-type wells; and
the first memory transistor and the first and second switch transistors are all n-channel transistors.
5. The non-volatile memory cell of claim 4 wherein the semiconductor body is an n-type well disposed in a p-type semiconductor substrate.
6. The non-volatile memory cell of claim 5 , further including an n-type isolating well disposed between and spaced apart from the first memory-transistor well and the first switch-transistor well, the n-type isolating well having a doping level higher than that of the semiconductor body.
7. The non-volatile memory cell of claim 6 , further including a deep n-type well, disposed below the n-type isolating well, and having a depth sufficient to prevent leakage between the first memory-transistor well and the first switch-transistor well.
8. The non-volatile memory cell of claim 5 , further including:
an enhanced p-type doped region at peripheral edges of the first memory-transistor well and the first switch-transistor well;
n-type annular wells disposed at the peripheral edges of the first memory-transistor well and the first switch-transistor well; and
deep n-type wells disposed under the n-type annular wells.
9. The non-volatile memory cell of claim 1 wherein the first memory-transistor well and the first switch-transistor well are separated by a deep trench isolation region.
10. The non-volatile memory cell of claim 1 , further including:
a second switch-transistor well disposed within the semiconductor body to a second side of the first memory-transistor well opposite the first side and electrically isolated from the first memory-transistor well;
a third switch transistor formed within the second switch-transistor well region and including spaced-apart source and drain regions;
a fourth switch transistor formed within the second switch-transistor well region and including spaced-apart source and drain regions;
the first floating gate insulated from and self aligned with the source and drain regions of the third and fourth switch transistors; and
the first control gate disposed above and self aligned with the source and drain regions of the third and fourth switch transistors.
11. The non-volatile memory cell of claim 1 , further including:
a second memory transistor formed within the first memory-transistor well and including spaced-apart source and drain regions;
a fifth switch transistor formed within the first switch-transistor well and including spaced-apart source and drain regions;
a sixth switch transistor formed within the first switch-transistor well and including spaced-apart source and drain regions;
a second floating gate insulated from and self aligned with the source and drain regions of the second memory transistor and the fifth and sixth switch transistors; and
a second control gate disposed above and self aligned with the second floating gate and with the source and drain regions of the second memory transistor and the fifth and sixth switch transistors.
12. The non-volatile memory cell of claim 11 wherein:
the first memory transistor and the second memory transistor have a common source region;
the first switch transistor and the fifth switch transistor have a common source region; and
the second switch transistor and the sixth switch transistor have a common source region.
13. The non-volatile memory cell of claim 11 , further including:
a seventh switch transistor formed within the second switch-transistor well and including spaced-apart source and drain regions;
an eighth switch transistor formed within the second switch-transistor well and including spaced-apart source and drain regions;
the second floating gate insulated from and self aligned with the source and drain regions of the seventh and eighth switch transistors; and
the second control gate disposed above and self aligned with the source and drain regions of the seventh and eighth switch transistors.
14. The non-volatile memory cell of claim 13 wherein:
the first memory transistor and the second memory transistor have a common source region;
the first switch transistor and the fifth switch transistor have a common source region;
the second switch transistor and the sixth switch transistor have a common source region;
the third switch transistor and the seventh switch transistor have a common source region;
the fourth switch transistor and the eighth switch transistor have a common source region.
15. The non-volatile memory cell of claim 13 , wherein:
the first memory-transistor well is optimized for memory-transistor characteristics and
the first and second switch-transistor wells are optimized for switch-transistor characteristics.
16. The non-volatile memory cell of claim 13 , wherein the first memory-transistor well and the first and second switch-transistor wells are formed to different depths.
17. The non-volatile memory cell of claim 13 wherein:
the semiconductor body is n-type;
the first memory-transistor well and the first and second switch-transistor wells are all p-type wells; and
all of the memory transistors and the switch transistors are all n-channel transistors.
18. The non-volatile memory cell of claim 17 , further including an n-type isolating well disposed between and spaced apart from the first memory-transistor well and the first and second switch-transistor wells, the n-type isolating well having a doping level higher than that of the semiconductor body.
19. The non-volatile memory cell of claim 18 , further including a deep n-type well, disposed below the n-type isolating well, and having a depth sufficient to prevent leakage between the first memory-transistor well and the first and second switch-transistor wells.
20. The non-volatile memory cell of claim 17 , further including:
an enhanced p-type doped region at peripheral edges of the first memory-transistor well and the first and second switch-transistor wells;
n-type annular wells disposed at the peripheral edges of the first memory-transistor well and the first and second switch-transistor wells; and
deep n-type wells disposed under the n-type annular wells.
21. The non-volatile memory cell of claim 17 wherein the first memory-transistor well and the first and second switch-transistor wells are separated by a deep trench isolation region.
22. The non-volatile memory cell of claim 17 , further including an n-type isolating well disposed between and spaced apart from the first memory-transistor well and the first switch-transistor well, the n-type isolating well having a doping level higher than that of the semiconductor body.
23. The non-volatile memory cell of claim 18 , further including a deep n-type well, disposed below the n-type isolating well, and having a depth sufficient to prevent leakage between the first memory-transistor well and the first switch-transistor well.
24. The non-volatile memory cell of claim 17 , further including:
an enhanced p-type doped region at peripheral edges of the first memory-transistor well and the first switch-transistor well;
n-type annular wells disposed at the peripheral edges of the first memory-transistor well and the first switch-transistor well; and
deep n-type wells disposed under the n-type annular wells.
25. The non-volatile memory cell of claim 11 wherein the first memory-transistor well and the first switch-transistor well are separated by a deep trench isolation region.