Circuits and methods for testing FPGA routing switches

1. In an FPGA architecture containing a routing multiplexer having an output and a plurality of inputs including a tie-off input that is coupled to a constant during normal operation, a method for testing the routing multiplexer comprising:

coupling one input of the routing multiplexer other than the tie-off input to the output of the routing multiplexer;

placing a signal on the one input of the routing multiplexer;

coupling the tie-off input to the output of the routing multiplexer; and

coupling the tie-off input of the routing multiplexer to a sensing circuit to observe the output of the routing multiplexer.

2. In an FPGA architecture containing a routing multiplexer having an output and a plurality of inputs including a tie-off input that is coupled to a constant during normal operation, a method for testing the routing multiplexer comprising:

coupling the tie-off input to the output of the routing multiplexer;

placing a test signal on an input of the routing multiplexer other than the tie-off input of the routing multiplexer; and

coupling the output of the routing multiplexer to a sensing circuit to observe the output of the routing multiplexer.

3. In an FPGA architecture including multiplexers formed from non-volatile switches having control gates coupled to word lines, each word line associated with a row, the multiplexers having outputs coupled to wiring tracks through buffers having controllable ground connections, a first plurality of the non-volatile switches being routing switches coupling signals into the multiplexer from routing tracks, and a second plurality of the non-volatile switches being tie-off switches coupleable to one of a plurality of bit lines and coupled to a constant during normal operation, each bit line associated with a column, a method of testing for routing switches that are stuck open or tracks that are open comprising:

forcing all non-volatile switches to an off state;

asserting a test enable signal to force all buffer outputs to a logic high level;

selecting a multiplexer having a tie-off switch;

asserting a turn-on voltage for the tie-off switch onto a word line for the row containing the tie-off switch;

coupling the tie-off switch to a bit line bit line for a column containing the tie-off switch;

individually for each routing switch in the multiplexer:

turning on the routing switch and sensing the bit line associated with the tie-off switch; and

determining that the routing switch is stuck open or the routing track from which it receives a signal is open if the bit line associated with the tie-off switch is not pulled high.

4. The method of claim 3 further including de-asserting the test enable signal, turning off the routing switch, and turning off the tie-off switch.

5. The method of claim 3 wherein selecting a multiplexer having a tie-off switch, asserting a turn-on voltage for the tie-off switch onto a word line for the row containing the tie-off switch, coupling the tie-off switch to a bit line bit line for a column containing the tie-off switch, individually for each routing switch in the multiplexer, turning on the tie-off switch and sensing the bit line associated with the tie-off switch; and determining that the routing switch is stuck open or the routing track from which it receives a signal is open if the bit line associated with the tie-off switch is not pulled high are performed for each multiplexer having a tie-off switch.

6. The method of claim 3 wherein more than one multiplexer having a tie-off switch is simultaneously selected; and

turning on the routing switch is performed for more than one multiplexer simultaneously.

7. In an FPGA architecture including multiplexers formed from non-volatile switches having control gates coupled to word lines, each word line associated with a row, the multiplexers having outputs coupled to wiring tracks through buffers having controllable ground connections, a first plurality of the non-volatile switches being routing switches coupling signals into the multiplexer from routing tracks, and a second plurality of the non-volatile switches being tie-off switches coupleable to one of a plurality of bit lines and coupled to a constant during normal operation, each bit line associated with a column, a method of testing for resistive switches or tracks comprising:

forcing all non-volatile switches to an off state;

asserting a test enable signal to force all buffer outputs to a logic high level;

selecting a multiplexer having a tie-off switch;

asserting a turn-on voltage for the tie-off switch onto a word line for the row containing the tie-off switch;

coupling the tie-off switch to a bit line bit line for a column containing the tie-off switch;

individually for each routing switch in the multiplexer:

turning on the routing switch; and

determining that the routing switch is resistive or the routing track from which it receives a signal is resistive if a current required to force the bit line associated with the tie-off switch to ground is above a selected current threshold.

8. The method of claim 7 wherein the selected current threshold is at least one half a typical current where there is no resistive defect.

9. The method of claim 7 wherein more than one multiplexer having a tie-off switch is simultaneously selected; and

turning on the routing switch is performed for more than one multiplexer simultaneously.

10. In an FPGA architecture including multiplexers formed from non-volatile switches having control gates coupled to word lines, each word line associated with a row, the multiplexers having outputs coupled to wiring tracks through buffers having controllable ground connections, a first plurality of the non-volatile switches being routing switches coupling signals into the multiplexer from routing tracks, and a second plurality of the non-volatile switches being tie-off switches coupleable to one of a plurality of bit lines and coupled to a constant during normal operation, each bit line associated with a column, a method of testing for routing switches that are stuck closed or any other shorts between a routing track and a non-corresponding buffer input comprising:

forcing all non-volatile switches to an off state;

asserting a test enable signal to force all buffer outputs to a logic high level;

selecting a multiplexer having a tie-off switch;

asserting a turn-on voltage for a tie-off switch in the selected multiplexer onto a word line for the row containing the tie-off switch;

sensing the voltage on the bit line of the column associated with the tie-off switch; and

determining that a routing switch in the selected multiplexer is stuck closed or any short circuits exist between a routing track and a non-corresponding buffer input associated with the selected multiplexer if the bit line of the column associated with the tie-off switch is pulled to a high logic level.

11. The method of claim 10 further including de-asserting the test enable signal, turning off the tie-off switch.

12. The method of claim 10 wherein at least two rows are turned on simultaneously provided that turning on at least two rows does not create a path from any track T i to any bit line B x in the absence of stuck-closed switches.