Inverting flip-flop for use in field programmable gate arrays
View Patent ↗A flip-flop for use in a field programmable gate array integrated circuit device is disclosed. The flip-flop comprises a data output terminal coupled to a first programmable routing element, a data input terminal coupled to a second programmable routing element, and a clock input terminal, wherein a signal appearing at the data output terminal in response to a signal applied to the clock input terminal has the opposite logical polarity with respect to the corresponding logical signal applied to the data input terminal.
1. A flip-flop circuit for use in a field programmable gate array integrated circuit device, the flip-flop circuit comprising:
a data storage element;
a data output terminal coupled to the data storage element and to a first programmable routing element;
a probe circuit coupled to the data output terminal;
a data input terminal coupled to the data storage element and to a second programmable routing element; and
a clock input terminal coupled to the data storage element, wherein a signal appearing at the data output terminal in response to a signal applied to the clock input terminal has the opposite logical polarity with respect to the corresponding logical signal applied to the data input terminal.
2. A circuit for use in a programmable logic integrated circuit device, the circuit connected to a programmable logic routing fabric, the circuit comprising:
a first multiplexer;
a function generator element including at least one input and an output;
a second multiplexer;
a data storage element including a data input, a data output, and an inverting multiplexer; and
a clock input coupled to the data storage element, wherein:
the first multiplexer receives a first input signal from the output of the data storage element and a second input signal from the programmable logic routing fabric;
the input of the function generator element receives a signal from an output of the first multiplexer;
the second multiplexer receives as a first input signal the second input signal to the first multiplexer and as a second input signal, the output of the function generator element;
the inverting multiplexer receives a first input from the output of the data storage element and a second input from the data output of the second multiplexer; and
a signal output by the data output of the data storage element in response to a signal applied to the clock input has an opposite logical polarity with respect to a signal received by the second input of the inverting multiplexer.
3. The circuit of claim 2 , further comprising an enable input terminal coupled to the data storage element.
4. The circuit of claim 2 , further comprising a probe circuit coupled to the data output of the data storage element.