Flash-based FPGA with secure reprogramming
View Patent ↗A flash-based programmable integrated circuit includes programmable circuitry, a flash memory array coupled to the programmable circuitry for configuring it, flash programming circuitry for programming the flash memory array, and an on-chip intelligence, such as a microcontroller or state machine, coupled to the programming circuitry to program the flash memory from off-chip data supplied via an I/O pad, or to refresh the data stored in the flash memory to prevent it from degrading.
1. A method for refreshing the flash memory of a flash-based programmable logic device including:
storing a decryption key on the integrated circuit;
taking the integrated circuit out of normal operating mode;
performing a current row operation including:
generating refresh data by one of reading the current row configuration data from the memory and reading encrypted data from a flash data I/O pad on the integrated circuit and decrypting the encrypted data using the decryption key;
erasing flash memory cells in the row;
programming the memory cells in the current row from the refresh data;
if the current row is not the last row in the memory, performing the current row operation on the next row to be refreshed; and
returning the integrated circuit to normal operation if the current row was the last row to be refreshed.
2. The method of claim 1 , further comprising:
setting a row counter to zero;
after programming the memory cells in the current row, determining whether the current row is the last row in the memory;
if the current row is not the last row in the memory, incrementing the row count and repeating performance of the current row operation.
3. The method of claim 1 , wherein erasing the flash memory cells in the row comprises erasing all the flash memory cells in the row.
4. The method of claim 3 , further comprising programming any previously unprogrammed memory cells in the current row before erasing all the flash memory cells in the row.
5. A method for reprogramming the flash memory of a flash-based programmable logic device including:
taking the integrated circuit out of normal operating mode;
performing a current row operation including:
erasing flash memory cells in the row;
loading and decrypting encrypted row configuration data for the current row;
programming the memory cells in the current row from the loaded and decrypted row configuration data;
if the current row is not the last row to be reprogrammed performing the current row operation on the next row to be reprogrammed; and
returning the integrated circuit to normal operation if the current row was the last row to be reprogrammed.
6. The method of claim 5 , further comprising:
setting a row counter to zero;
after programming the memory cells in the current row, determining whether the current row is the last row in the memory;
if the current row is not the last row in the memory, incrementing the row count and repeating performance of the current row operation.
7. The method of claim 5 , wherein erasing the flash memory cells in the row comprises erasing all the flash memory cells in the row.
8. The method of claim 7 , further comprising programming any previously unprogrammed memory cells in the current row before erasing all the flash memory cells in the row.