Non-volatile two-transistor programmable logic cell and array layout
A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory transistor including spaced-apart source and drain regions is formed within the memory-transistor well. A switch transistor including spaced-apart source and drain regions is formed within the switch-transistor well region. A floating gate is insulated from and self aligned with the source and drain regions of the memory transistor and switch transistor. A control gate is disposed above and aligned to the floating gate and with the source and drain regions of the memory transistor and the switch transistor.
1. A two-transistor non-volatile memory cell including:
a semiconductor body;
a memory-transistor well disposed within the semiconductor body;
a switch-transistor well disposed within the semiconductor body and electrically isolated from the memory transistor well by an isolation well formed in the semiconductor body;
a memory transistor formed within the memory-transistor well and including spaced-apart source and drain regions;
a switch transistor formed within the switch-transistor well region and including spaced-apart source and drain regions;
a floating gate insulated from and self aligned with the source and drain regions of the memory transistor and the switch transistor; and
a control gate disposed above and self aligned with respect to the floating gate and with the source and drain regions of the memory transistor and the switch transistor.
2. The two-transistor non-volatile memory cell of claim 1 , further including at least one additional switch transistor disposed in a switch-transistor well and sharing a floating gate and a control gate with the memory transistor.
3. The two-transistor non-volatile memory cell of claim 1 wherein:
the semiconductor body is an n-type well;
the memory-transistor well and the switch transistor well are both p-type wells; and
the memory transistor and the switch transistor are both n-channel transistors.
4. The two-transistor non-volatile memory cell of claim 3 wherein the semiconductor body is an n-type well disposed in a p-type semiconductor substrate.
5. The two-transistor non-volatile memory cell of claim 3 wherein the semiconductor body is an n-type well formed in a semiconductor substrate.
6. The two-transistor non-volatile memory cell of claim 5 , further including at least one additional switch transistor disposed in a switch-transistor p-type well and sharing a floating gate and a control gate with the memory transistor.
7. The two-transistor non-volatile memory cell of claim 3 wherein:
the semiconductor body is a n-type well formed in a semiconductor substrate; and
the switch-transistor p-type well is spaced apart from the memory-transistor p-type well by the n-type well and
the isolation well is a second n-type well formed in the n-type well between the switch-transistor p-type well and the memory-transistor p-type well.
8. The two-transistor non-volatile memory cell of claim 7 , further including at least one additional switch transistor disposed in a switch-transistor p-type well and sharing a floating gate and a control gate with the memory transistor.
9. The two-transistor non-volatile memory cell of claim 7 wherein edges of the second n-type well are spaced apart from edges of the memory-transistor p-type well and the switch-transistor p-type well.
10. The two-transistor non-volatile memory cell of claim 1 wherein the memory-transistor wells are optimized for memory-transistor characteristics and the switch-transistor wells are optimized for switch-transistor characteristics.
11. The two-transistor non-volatile memory cell of claim 1 wherein the memory-transistor well and the switch-transistor well are formed to different depths.
12. An array of two-transistor non-volatile memory cells including:
a semiconductor body;
at least one memory-transistor well disposed within the semiconductor body;
at least one switch-transistor well disposed within the semiconductor body spaced apart from and electrically isolated from the at least one memory transistor well by an isolation well formed in the semiconductor body;
a plurality of memory transistors formed within the at least one memory-transistor well, each including spaced-apart source and drain regions;
a plurality of switch transistors formed within the at least one switch-transistor well region, each associated with one of the memory transistors and including spaced-apart source and drain regions;
a floating gate associated with each memory transistor, each floating gate insulated from and self-aligned with the source and drain regions of the switch transistor with which it is associated; and
a control gate associated with each memory transistor, each control gate disposed above and self aligned with its floating gate and with the source and drain regions of the at least one switch transistor with which it is associated.
13. The array of claim 12 , further including at least one additional switch transistor disposed in a switch-transistor well and sharing a floating gate and a control gate with one of the memory transistors.
14. The array of claim 12 wherein:
the semiconductor body is an n-type well;
the at least one memory-transistor well and the at least one switch transistor well are both p-type wells; and
the memory transistors and the switch transistors are all n-channel transistors.
15. The array of claim 14 wherein the semiconductor body is an n-type well disposed in a p-type semiconductor substrate.
16. The array of claim 14 wherein:
the semiconductor body is a n-type well formed in a semiconductor substrate; and
the at least one switch-transistor p-type well is spaced apart from the at least one memory-transistor p-type well and is isolated from the memory transistor p-type well by an n-type isolation well disposed in the n-type well between the at least one switch-transistor p-type well and the at least one memory-transistor p-type well.
17. The array of claim 16 , further including at least one additional switch transistor disposed in a switch-transistor p-type well and sharing a floating gate and a control gate with a memory transistor.
18. The array of claim 17 , further including at least one additional switch transistor disposed in a switch-transistor p-type well and sharing a floating gate and a control gate with a memory transistor.
19. The array of claim 14 wherein edges of the low-voltage n-type well are spaced apart from edges of the memory-transistor p-type well and the switch-transistor p-type well.
20. The array of claim 12 wherein the at least one memory-transistor well and the at least one switch-transistor well are formed to different depths.
21. The array of claim 12 wherein the at least one memory-transistor well is optimized for memory-transistor characteristics and the at least one switch-transistor well is optimized for switch-transistor characteristics.