Staggered I/O groups for integrated circuits
View Patent ↗An I/O scheme for an integrated circuit includes a group layout cell. The group layout cell includes a plurality of signal I/O pads. A driver circuit is coupled to each signal I/O pad. The group layout cell also includes two I/O driver-circuit power-supply pads. ESD protection circuitry is coupled to the plurality of driver circuits. The signal I/O pads and the I/O driver-circuit power-supply pads are arranged in rows. The rows may be regular or staggered.
1. A layout for an I/O scheme for an integrated circuit including:
a group layout cell including:
a plurality of bonding pads including at least one supply pad and a plurality of signal I/O pads;
a plurality of I/O cells, each I/O cell including an I/O driver circuit, each I/O cell connected to at least one of the plurality of signal I/O pads;
the I/O cells having a pitch that is larger than a pitch of the bonding pads.
2. The layout of claim 1 wherein the bonding pads are arranged in two rows.
3. The layout of claim 2 wherein the bonding pads in the two rows are aligned with one another and the pitch of the bonding pads is the periodicity of two adjacent bonding pads in one row divided by the number of rows.
4. The layout of claim 2 wherein the bonding pads in the two rows are staggered from one another.
5. The layout of claim 4 wherein adjacent signal I/O pads that are in the same row are spaced according to an inline pitch and adjacent signal I/O pads that are in different rows are spaced according to a staggered pitch, the inline pitch being greater than the staggered pitch.
6. The layout of claim 5 wherein the inline pitch is about 47 um and the staggered pitch is about 35 um.
7. The layout of claim 5 wherein adjacent signal I/O pads and supply pads that are in different rows are spaced according to about one half of the inline pitch.
8. The layout of claim 1 wherein the plurality of signal I/O pads includes four signal I/O pads.
9. The layout of claim 8 wherein the plurality of signal I/O pads and the two supply pads are arranged in two rows.
10. The layout of claim 9 wherein the two rows of bonding pads are aligned with one another and the pitch of the bonding pads is the periodicity of two adjacent bonding pads in one row divided by the number of rows.
11. The layout of claim 9 wherein the two rows of bonding pads are staggered from one another.
12. The layout of claim 1 wherein the at least one supply pad includes two I/O driver-circuit supply pads.
13. The layout of claim 1 where the I/O scheme is a wire-bonding I/O scheme.
14. A layout for an I/O scheme for an integrated circuit including:
a first group layout cell having a plurality of signal I/O pads, a plurality of driver circuits, one driver circuit coupled to each signal I/O pad, and two I/O driver-circuit power supply pads, the plurality of signal I/O pads and the two I/O driver-circuit supply pads arranged in two rows;
a second group layout cell having a plurality of signal I/O pads, a plurality of driver circuits, one driver circuit coupled to each signal I/O pad, and two I/O driver-circuit supply pads, the plurality of signal I/O pads and the two I/O driver-circuit supply pads arranged in two rows;
wherein the two rows of bonding pads in both the first group layout cell and the second group layout cell are staggered from one another, adjacent signal I/O pads that are in the same row are spaced according to an inline pitch and adjacent signal I/O pads that are in different rows are spaced according to a staggered pitch, the inline pitch being greater than the staggered pitch, and adjacent signal I/O pads that are in corresponding rows of the first and second group layout cells are spaced according to the inline pitch.
15. A layout of claim 14 , wherein adjacent supply pads in corresponding rows of the first and second group layout cells are spaced according to the inline pitch.
16. A layout for an I/O scheme for an integrated circuit including:
a group-cell area in the integrated circuit defining a group layout cell including:
a plurality of bonding pads disposed substantially within the group-cell area and including at least one supply pad and a plurality of signal I/O pads; and
a plurality of I/O cells, each I/O cell having an identical size and shape and disposed under the bonding pads, the plurality of I/O cells occupying all of the group-cell area, each I/O cell connected to at least one of the plurality of signal I/O pads, each of the plurality of signal I/O pads connected to only one of the I/O cells; and
circuitry within the group layout cell, the circuitry including an I/O driver circuit for each I/O cell and ESD protection circuitry for each bonding pad, the circuitry entirely disposed within the I/O cells.
17. The layout of claim 16 wherein the bonding pads are arranged in two rows.
18. The layout of claim 17 wherein the bonding pads in the two rows are aligned with one another.
19. The layout of claim 17 wherein the bonding pads in the two rows are staggered from one another.
20. The layout of claim 16 wherein the plurality of signal I/O pads includes four signal I/O pads.
21. The layout of claim 20 wherein the plurality of signal I/O pads and the two supply pads are arranged in two rows.
22. The layout of claim 21 wherein the two rows of bonding pads are aligned with one another.
23. A layout for an I/O scheme for an integrated circuit including:
a group layout cell including:
a plurality of wire-bonding pads including at least one supply pad and a plurality of signal I/O pads;
a plurality of I/O cells, each I/O cell including an I/O driver circuit, each I/O cell connected to at least one of the plurality of signal I/O pads;
wherein a position along an edge of the integrated circuit die of an I/O cell relative to a position along the edge of an I/O signal pad associated with the I/O cell varies from one I/O cell to another.
24. A layout for an I/O scheme for an integrated circuit including:
a group layout cell including:
a plurality of wire-bonding pads including at least one supply pad and a plurality of signal I/O pads;
a plurality of I/O cells, each I/O cell including an I/O driver circuit, each I/O cell connected to at least one of the plurality of signal I/O pads;
wherein the I/O cells have a minimum pitch that is larger than a minimum pitch of the signal I/O pads.
25. A layout for an I/O scheme for an integrated circuit including:
a group layout cell including:
a plurality of wire-bonding pads including at least one supply pad and a plurality of signal I/O pads, a ratio of supply pads to signal I/O pads is not equal to 1;
a plurality of I/O cells, each I/O cell including an I/O driver circuit, each I/O cell connected to at least one of the plurality of signal I/O pads;
wherein the I/O cells have a uniform pitch that is an integer multiple of an effective pitch of the signal I/O pads.
26. A layout for an I/O scheme for an integrated circuit including:
a group layout cell including:
a plurality of wire-bonding pads including at least one I/O supply pad and a plurality of signal I/O pads, the number of I/O supply pads being half the total number of wire-bonding pads;
a plurality of I/O cells, each I/O cell including an I/O driver circuit, each I/O cell connected to at least one of the plurality of signal I/O pads;
wherein the I/O cells have a uniform pitch that is an integer multiple of an effective pitch of the signal I/O pads.
27. A layout for an I/O scheme for an integrated circuit including:
a group layout cell including:
a plurality of wire-bonding pads including at least one supply pad and a plurality of signal I/O pads, the wire-bonding pads arranged in at least three two rows;
a plurality of I/O cells, each I/O cell including an I/O driver circuit, each I/O cell connected to at least one of the plurality of signal I/O pads;
wherein the I/O cells have a uniform pitch that is an integer multiple of an effective pitch of the signal I/O pads.
28. A layout for an I/O scheme for an integrated circuit including:
a group layout cell including:
a plurality of wire-bonding pads including at least one I/O supply pad and a plurality of signal I/O pads, the wire-bonding pads arranged in at least two rows in which the wire bonding pads are staggered in adjacent rows;
a plurality of I/O cells, each I/O cell including an I/O driver circuit, each I/O cell connected to at least one of the plurality of signal I/O pads;
wherein the I/O cells have a uniform pitch that is an integer multiple of an effective pitch of the signal I/O pads.