SRAM cell controlled by flash memory cell
View Patent ↗First and second complimentary static random-access-memory cell bit lines are coupled to first and second bit nodes through first and second access transistors controlled by a word line. A first inverter has an input coupled to the first bit node and an output coupled to the second bit node. A second inverter has an input coupled to the second bit node and an output coupled to the first bit node through a first transistor switch. A transistor switch is coupled between the output of a non-volatile memory cell and the first bit node. A control circuit coupled to the gate of the transistor switch. Either the drive level of the non-volatile memory cell is selected to overpower the output of the second inverter or the second inverter is decoupled from the first bit node while the output of the non-volatile memory cell is coupled to the first bit node.
1. A multi-purpose static random-access-memory cell controllable by a non-volatile memory cell comprising:
a static random-access-memory cell coupled between first and second complimentary static random-access-memory cell bit nodes;
a static random-access-memory cell word line;
first and second complimentary static random-access-memory cell bit lines respectively coupled to the first and second complimentary static random-access-memory cell bit nodes through first and second access transistors, each of the first and second access transistors having a gate coupled to the static random-access-memory cell word line;
a configuration word line;
first and second complimentary configuration bit lines respectively coupled to the first and second complimentary static random-access-memory cell bit nodes through third and fourth access transistors, each of the third and fourth access transistors having a gate coupled to the configuration word line;
a serial shift register stage having first and second complementary clock lines, said serial shift register stage coupled to the first and second complimentary static random-access-memory cell bit nodes;
a non-volatile memory cell having an output;
a complementing transistor coupled to the output of the non-volatile memory;
a first transistor switch coupled between the output of the non-volatile memory cell and the first static random-access-memory cell bit node, the first transistor switch having a gate;
a second transistor switch coupled between the output of the complementing transistor and the second static random-access-memory cell bit node, the second transistor switch having a gate;
a control circuit coupled to the gates of the first and second transistor switches.
2. The multi-purpose static random-access-memory cell of claim 1 , wherein the output of the non-volatile memory cell and the complementing transistor each have a drive level selected to force the state of the static random-access-memory cell.
3. The multi-purpose static random-access-memory cell of claim 1 , wherein the second transistor switch is coupled between the output of the complementing transistor and the first static random-access-memory cell bit node.
4. The multi-purpose static random-access-memory cell of claim 1 , further comprising:
a first inverter having an input connected to the first static random-access-memory cell bit node and an output connected to the second static random-access-memory cell bit node; and
a second inverter having an input connected to the second static random-access-memory cell bit node and an output connected to the first static random-access-memory cell bit node,
wherein the output of first inverter is connected to the input of the second inverter, and the output of the second inverter is connected to the input of the first inverter.
5. The multi-purpose static random-access-memory cell of claim 4 , wherein the output of the non-volatile memory cell is buffered to overpower the output of the second inverter.
6. The multi-purpose static random-access-memory cell of claim 1 , wherein the non-volatile memory cell is a flash memory cell.
7. The multi-purpose static random-access-memory cell of claim 1 , wherein the first complementary clock line is coupled to the first complimentary static random-access-memory cell bit node and the second complementary clock line is coupled to the second complimentary static random-access-memory cell bit node.
8. The multi-purpose static random-access-memory cell of claim 1 , wherein the first and second access transistors are n-channel MOS transistors.
9. The multi-purpose static random-access-memory cell of claim 1 , wherein the third and fourth access transistors are n-channel MOS transistors.
10. The multi-purpose static random-access-memory cell of claim 1 , wherein the first and second transistor switches are n-channel MOS transistors.
11. The multi-purpose static random-access-memory cell of claim 1 , wherein the complementing transistor is an n-channel MOS transistors.