Quadratic and cubic compensation of sigma-delta D/A and A/D converters

1. A method for compensating a sigma-delta modulator having an input and an output, comprising:

providing a binary word Q that represents a desired amount of quadratic compensation;

encoding from the output of the sigma-delta modulator a low-resolution signal having a value and a duty factor that together approximate a quadratic function of the sigma-delta modulator input;

multiplying the binary word Q by the low-resolution signal to generate a resultant number; and

adding the resultant number to one of the sigma-delta modulator input and the sigma-delta modulator output.

2. The method of claim 1 , wherein: the low-resolution signal is a one-bit signal.

3. The method of claim 2 , wherein encoding from the output of the sigma-delta modulator a low-resolution signal having a value and a duty factor that together approximate a quadratic function of the sigma-delta modulator input includes:

examining a current output bit and an immediately previous output bit of the sigma-delta modulator; and

generating a one-bit signal having a binary value of one when the current output bit and the immediately previous output bit of the sigma-delta modulator are the same and having a binary value of zero when the current output bit and the immediately previous output bit of the sigma-delta modulator are different.

4. The method of claim 3 , wherein generating the one-bit signal includes:

storing the immediately previous output bit of the sigma-delta modulator for one clock cycle; and

performing an XNOR function on the current output bit of the sigma-delta modulator and the immediately previous output bit of the sigma-delta modulator.

5. The method of claim 1 , wherein providing a binary word Q that represents a desired amount of quadratic compensation includes:

storing the binary word Q in non-volatile memory.

6. The method of claim 1 , further comprising:

applying cubic compensation to one of the sigma-delta modulator input and the sigma-delta modulator output.

7. The method of claim 6 , wherein applying cubic compensation to one of the sigma-delta modulator input and the sigma-delta modulator output includes:

providing a binary word C that represents a desired amount of cubic compensation;

examining a current output bit, a first immediately previous output bit, and a second immediately previous output bit of the sigma-delta modulator; and

adding C to one of the modulator input and the modulator output when all of:

the current output bit,

a first immediately previous output bit, and

a second immediately previous output bit

of the sigma-delta modulator have binary value zero; and

when only one of:

the current output bit,

the first immediately previous output bit, and

the second immediately previous output bit

of the sigma-delta modulator has binary value zero; and

adding a complement of C to the modulator output when all of:

the current output bit,

the first immediately previous output bit, and

the second immediately previous output bit of the sigma-delta modulator have binary value one; and when only one of:

the current output bit,

the first immediately previous output bit, and

the second immediately previous output bit of the sigma-delta modulator has binary value one.

8. A method for compensating a sigma-delta modulator having an input and an output including:

providing a binary word C that represents a desired amount of cubic compensation;

encoding from the output of the modulator a low-resolution signal having a value and a duty factor that together approximate a cubic function of the sigma-delta modulator input;

multiplying the binary word C by the low-resolution signal to create a resultant number;

applying the resultant number to one of the sigma-delta modulator input and the sigma-delta modulator output.

9. The method of claim 8 , wherein providing a binary word C having a duty factor that represents a desired amount of cubic compensation includes storing the binary word C in non-volatile memory.

10. The method of claim 8 , further comprising:

examining a current output bit, a first immediately previous output bit, and a second immediately previous output bit of the sigma-delta modulator; and

adding C to one of the modulator input and the modulator output; when all of:

the current output bit,

a first immediately previous output bit, and

a second immediately previous output bit

of the sigma-delta modulator have binary value zero; and when

only one of:

the current output bit,

the first immediately previous output bit, and

the second immediately previous output bit

of the sigma-delta modulator has binary value zero; and

adding the complement of C to the modulator output; when

all of:

the current output bit,

the first immediately previous output bit, and

the second immediately previous output bit of the sigma-delta modulator have binary value one; and when

only one of:

the current output bit,

the first immediately previous output bit, and

the second immediately previous output bit of the sigma-delta modulator has the value one.

11. A method for compensating a sigma-delta modulator having an input and an output comprising:

providing a binary word Q that represents a desired amount of quadratic compensation;

providing a binary word C that represents a desired amount of cubic compensation;

examining a current output bit, a first immediately previous output bit, and a second immediately previous output bit of the sigma-delta modulator; and

selecting a value, wherein:

the value is C when all of:

the current output bit,

the first immediately previous output bit, and

the second immediately previous output bit

of the sigma-delta modulator have binary value zero;

the value is a complement of C when all of:

the current output bit,

the first immediately previous output bit, and

the second immediately previous output bit

of the sigma-delta modulator have binary value one; and

otherwise the value is Q; and

applying the selected value to one of the sigma-delta modulator input and the sigma-delta modulator output.

12. The method of claim 11 , wherein:

providing a binary word Q that represents a desired amount of quadratic compensation includes storing the binary word Q in non-volatile memory; and

providing a binary word C that represents a desired amount of cubic compensation includes storing the binary word C in non-volatile memory.

13. A method for compensating a sigma-delta modulator having an input and an output comprising:

providing at least one of a binary word Q that represents a desired amount of quadratic compensation and a binary word C that represents a desired amount of cubic compensation;

providing a compensation algorithm for applying from:

the current output of the sigma-delta modulator; and

at least one immediately-previous output of the sigma-delta-modulator:

compensation related to at least one of Q and C;

examining a current output of the sigma-delta modulator and at least one immediately-previous output of the sigma-delta-modulator; and

applying compensation related to at least one of Q and C in accordance with the algorithm to at least one of the sigma-delta modulator input and the sigma-delta modulator output.

14. The method of claim 13 , wherein providing at least one of a binary word Q that represents a desired amount of quadratic compensation and a binary word C that represents a desired amount of cubic compensation includes storing the at least one of the binary word Q and the binary word C in non-volatile memory.

15. The method of claim 13 , wherein:

providing a compensation algorithm for applying from the current output of the sigma-delta modulator and at least one immediately-previous output of the sigma-delta-modulator compensation related to at least one of Q and C includes:

encoding a quadratic and cubic compensation algorithm from the current output of the sigma-delta modulator and a selected number of immediately-previous outputs of the sigma-delta-modulator; and

examining the current output of the sigma-delta modulator and at least one immediately-previous output of the sigma-delta-modulator includes:

examining the current output of the sigma-delta modulator and a selected number of immediately previous outputs of the sigma-delta modulator.

16. The method of claim 15 , wherein:

the selected number of immediately-previous outputs is two.

17. The method of claim 15 , wherein:

the selected number of immediately-previous outputs is three.

18. A compensation circuit for a sigma-delta modulator comprising:

a shift register for storing at least one most-recent output bit from a sigma-delta modulator, the shift register having at least one output;

a storage location for storing a quadratic compensation value;

and

a logic unit having an output providing, in response to the at least one output of the shift register, one of:

the quadratic compensation value; and

one of a complement of the quadratic compensation value and a fixed constant value.

19. The compensation circuit for a sigma-delta modulator of claim 18 , wherein:

the logic unit comprises a multiplexer having at least one select input coupled to an output of the shift register, and a plurality of data inputs, each data input coupled to a node presenting one of:

the quadratic compensation value;

the complement of the quadratic compensation value, and

the fixed constant value.

20. A compensation circuit for a sigma-delta modulator comprising:

a shift register for storing at least one most-recent output bit from a sigma-delta modulator, the shift register having at least one output;

a first storage location for storing a cubic compensation value;

a second storage location for storing a fixed constant;

a complementing circuit having an input coupled to the first storage location and further having an output; and

a logic unit having an output providing, in response to the at least one output of the shift register, one of:

the cubic compensation value;

a complement of the cubic compensation value, and

the fixed constant value.

21. The compensation circuit for a sigma-delta modulator of claim 20 , wherein: the logic unit comprises a multiplexer having at least one select input coupled to an output of the shift register, and a plurality of data inputs, each data input coupled to a node presenting one of:

the cubic compensation value;

the complement of the cubic compensation value, and

the fixed constant value.

22. A compensation circuit for a sigma-delta modulator comprising:

a shift register for storing at least one most-recent output bit from a sigma-delta modulator, the shift register having at least one output;

a first storage location for storing a quadratic compensation value;

a second storage location for storing a cubic compensation value; and

a logic unit having an output providing, in response to the at least one output of the shift register, one of:

the quadratic compensation value;

the cubic compensation value; and

a linear combination of the quadratic compensation value and the cubic compensation value.

23. A method for processing an analog signal in a system-on-a-chip that includes a programmable logic circuit block and an A/D circuit block including a sigma-delta modulator, the method comprising:

receiving the analog signal in the A/D circuit block;

compensating the A/D sigma-delta modulator including:

providing a first binary word Q that represents a desired amount of quadratic compensation;

encoding from the output of the A/D sigma-delta modulator a first low-resolution signal having a value and a duty factor that together approximate a quadratic function of the A/D sigma-delta modulator input;

multiplying the first binary word Q by the first low-resolution signal to generate a first resultant number; and

adding the first resultant number to the A/D sigma-delta modulator output;

outputting a compensated digital signal from the A/D circuit block;

receiving the compensated digital signal in the programmable logic circuit block;

processing the compensated digital signal in the programmable logic circuit block.

24. The method of claim 23 , wherein the system-on-a-chip further includes a D/A circuit block including a sigma-delta modulator, the method further comprising:

outputting a processed digital signal from the programmable logic circuit block to the D/A circuit block;

compensating the D/A sigma-delta modulator including:

providing a second binary word Q that represents a desired amount of quadratic compensation;

encoding from the output of the D/A sigma-delta modulator a second low-resolution signal having a value and a duty factor that together approximate a quadratic function of the D/A sigma-delta modulator input;

multiplying the second binary word Q by the second low-resolution signal to generate a second resultant number; and

adding the second resultant number to the D/A sigma-delta modulator input;

outputting a compensated analog signal from the D/A circuit block.

25. A system-on-a-chip comprising:

an A/D converter circuit block including an A/D delta-sigma modulator and an A/D compensation circuit for the sigma-delta modulator, the A/D compensation circuit including:

an A/D shift register for storing at least one most-recent output bit from the A/D sigma-delta modulator, the shift register having at least one output;

an A/D storage location for storing an A/D quadratic compensation value; and

an A/D logic unit having an output providing, in response to the at least one output of the A/D shift register, one of:

the A/D quadratic compensation value; and

one of a complement of the A/D quadratic compensation value and a fixed constant value; and

a programmable logic circuit block coupled to the A/D converter circuit block.

26. The system-on-a-chip of claim 25 , further comprising: a D/A converter circuit block coupled to the programmable logic circuit block, the D/A converter circuit block including:

a D/A converter circuit block including a D/A delta-sigma modulator and a D/A compensation circuit for the D/A sigma-delta modulator, the D/A compensation circuit including:

a D/A shift register for storing at least one most-recent output bit from the D/A sigma-delta modulator, the D/A shift register having at least one output;

a D/A storage location for storing a D/A quadratic compensation value;

and

a D/A logic unit having an output providing, in response to the at least one output of the D/A shift register, one of:

the D/A quadratic compensation value; and

one of a complement of the D/A quadratic compensation value and a fixed constant value.