Non-volatile look-up table for an FPGA
View Patent ↗A non-volatile-memory-transistor based lookup table for an FPGA includes a n:1 multiplexer. A non-volatile memory transistor is coupled to each of the n inputs of the multiplexer. The multiplexer has x address inputs wherein 2 x =n as is known in the art. The output of the multiplexer is coupled to V CC through a pullup transistor. The gate of the pullup transistor is coupled to the output of an address transition detector circuit that has inputs coupled to the address inputs of the multiplexer. A sense amplifier is coupled to the output of the multiplexer.
1. A non-volatile-memory-transistor based lookup table for an FPGA including:
a multiplexer having a plurality of address inputs, a plurality of data inputs, and an output;
a pair of series-connected non-volatile memory transistors coupled to each of the data inputs of the multiplexer; and
a sense amplifier is coupled to the output of the multiplexer.
2. The non-volatile-memory-transistor based lookup table of claim 1 wherein the multiplexer has x address inputs and 2 X data inputs.
3. The non-volatile-memory-transistor based lookup table of claim 1 wherein the multiplexer has four address inputs and sixteen data inputs.
4. The non-volatile-memory-transistor based lookup table of claim 1 wherein each non-volatile memory transistor is a floating gate transistor.
5. The non-volatile-memory-transistor based lookup table of claim 1 wherein each non-volatile memory transistor is a nano-crystal transistor.
6. The non-volatile-memory-transistor based lookup table of claim 1 wherein each non-volatile memory transistor is a SONOS transistor.
7. A non-volatile-memory-transistor based lookup table for an FPGA including:
a multiplexer having x address inputs, 2 X data inputs, and an output;
a plurality of data-input circuits, each coupled to one of the data inputs of the multiplexer and including:
a first n-channel MOS transistor having a drain coupled to a power supply potential, a source coupled to the data input of the multiplexer, and a gate,
a second n-channel MOS transistor having a drain coupled to the data input of the multiplexer, a source coupled to ground, and a gate,
a first non-volatile memory cell having an output coupled to the gate of the first n-channel MOS transistor; and
a second non-volatile memory cell having an output coupled to the gate of the second n-channel MOS transistor;
and
a sense amplifier is coupled to the output of the multiplexer.
8. The non-volatile-memory-transistor based lookup table of claim 7 wherein the multiplexer has four address inputs and sixteen data inputs.
9. The non-volatile-memory-transistor based lookup table of claim 7 wherein each non-volatile memory cell includes a floating gate transistor.
10. The non-volatile-memory-transistor based lookup table of claim 7 wherein each non-volatile memory cell includes a nano-crystal transistor.
11. The non-volatile-memory-transistor based lookup table of claim 7 wherein each non-volatile memory cell includes a SONOS transistor.
12. A non-volatile-memory-transistor based lookup table for an FPGA including:
a multiplexer having 3 address inputs, 8 data inputs, and an output;
a plurality of data-input circuits, each coupled to one of the data inputs of the multiplexer and including:
a first non-volatile memory cell having an output coupled to the gate of a first n-channel MOS transistor, the first n-channel MOS transistor having a source coupled to the data input of the multiplexer and a drain coupled to a power supply potential;
a second non-volatile memory cell having an output coupled to the gate of a second n-channel MOS transistor, the second n-channel MOS transistor having a source coupled to the data input of the multiplexer and a drain coupled to an input signal;
a third non-volatile memory cell having an output coupled to the gate of a third n-channel MOS transistor, the third n-channel MOS transistor having a source coupled to the data input of the multiplexer and a drain coupled to the complement of the input signal; and
a fourth non-volatile memory cell having an output coupled to the gate of a fourth n-channel MOS transistor, the fourth n-channel MOS transistor having a source coupled to the data input of the multiplexer and a drain coupled to ground;
and
a sense amplifier is coupled to the output of the multiplexer.
13. The non-volatile-memory-transistor based lookup table of claim 12 wherein the multiplexer has four address inputs and sixteen data inputs.
14. The non-volatile-memory-transistor based lookup table of claim 12 wherein each non-volatile memory transistor is a floating gate transistor.
15. The non-volatile-memory-transistor based lookup table of claim 12 wherein each non-volatile memory transistor is a nano-crystal transistor.
16. The non-volatile-memory-transistor based lookup table of claim 12 wherein each non-volatile memory transistor is a SONOS transistor.